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公开(公告)号：US20250157518A1
公开(公告)日：2025-05-15
申请号：US18891518
申请日：2024-09-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hwayeong Lee , Seulji Song
Abstract: An operating method of a memory device includes, during a write operation, in a first time period, pre-charging a bit line connected to a memory cell with a ground voltage, during the write operation, in a second time period, applying a word line driving voltage to a word line corresponding to the bit line, in the second time period, applying a plate line driving voltage to a plate line connected to the memory cell, and in the second time period, maintaining a voltage applied to the bit line at the ground voltage.
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公开(公告)号：US12237047B2
公开(公告)日：2025-02-25
申请号：US18303937
申请日：2023-04-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hwan Kim , Suhee Jeon , Seulji Song
IPC: G11C7/10
Abstract: A method of reading data from a self-selecting memory includes generating a read pulse that has a polarity opposite to that of a write pulse. The write pulse writes data into a target memory cell in the self-selecting memory. The read pulse is applied to the target memory cell. The read pulse has a first edge that is a starting point of the read pulse and a second edge that is an ending point of the read pulse. A slope of the second edge of the read pulse is adjusted such that an undershoot or overshoot on the second edge of the read pulse increases.
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公开(公告)号：US20250008747A1
公开(公告)日：2025-01-02
申请号：US18537013
申请日：2023-12-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Suhyun Bang , Seulji Song , Youngsun Song
Abstract: A three-dimensional memory device includes a base insulating layer on a substrate, a stack structure including word lines and first interlayer insulating layers which are alternately stacked on the base insulating layer, and a second interlayer insulating layer on an uppermost one of the word lines, bit lines that are in the stack structure and spaced apart from each other in a first direction parallel to a top surface of the substrate, each bit line including a first portion that protrudes from a top surface of the stack structure and a second portion that are in the stack structure, an outer electrode on the stack structure and on the first portions of the bit lines, and a dielectric layer between the outer electrode and the first portion of the bit line and surrounding a side surface of the first portion of the bit line in plan view.
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公开(公告)号：US20210167130A1
公开(公告)日：2021-06-03
申请号：US16937963
申请日：2020-07-24
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kyusul PARK , Woohyun PARK , Ilmok PARK , Seulji Song
Abstract: A variable resistance memory device and a method of fabricating a variable resistance memory device, the device including first conductive lines extending in a first direction; second conductive lines extending in a second direction crossing the first direction; and memory cells at respective intersection points of the first conductive lines and the second conductive lines, wherein each of the memory cells includes a switching pattern, an intermediate electrode, a variable resistance pattern, and an upper electrode, which are between the first and second conductive lines and are connected in series; and a spacer structure including a first spacer and a second spacer, the first spacer being on a side surface of the upper electrode, and the second spacer covering the first spacer and a side surface of the variable resistance pattern such that the second spacer is in contact with the side surface of the variable resistance pattern.
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公开(公告)号：US20250015135A1
公开(公告)日：2025-01-09
申请号：US18732958
申请日：2024-06-04
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hwayeong Lee , Seulji Song
IPC: H01L29/08 , H01L29/24 , H01L29/423 , H01L29/78 , H10B12/00
Abstract: A vertical channel transistor includes a substrate having a bit line thereon, and a vertical channel layer including a first metal oxide, on the bit line. A lower insertion layer is provided, which extends between the bit line and a first end of the channel layer, and includes a second metal oxide having a greater bonding energy relative to the first metal oxide. A lower source/drain region is provided, which extends between the first end of the channel layer and the lower insertion layer, and includes a first metal dopant that is a reduced form of the first metal oxide. An upper source/drain region is provided, which is electrically connected to a second end of the channel layer, and includes the first metal dopant. An insulated gate line is provided on the channel layer.
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Patent Agency Ranking
公开(公告)号：US20240422994A1
公开(公告)日：2024-12-19
申请号：US18653689
申请日：2024-05-02
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Youngsun Song , Seulji Song
IPC: H10B63/00
Abstract: A semiconductor memory device includes a first source line extending in a first horizontal direction, a second source line extending on the first source line in the first horizontal direction, a plurality of word line plates arranged apart from each other in a vertical direction, between the first source line and the second source line, a vertical bit line configured to penetrate the plurality of word line plates and extending in the vertical direction, a selector arranged between the plurality of word line plates and the vertical bit line, a first vertical channel transistor arranged between the vertical bit line and the first source line, and a second vertical channel transistor arranged between the vertical bit line and the second source line.
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公开(公告)号：US11276821B2
公开(公告)日：2022-03-15
申请号：US16741936
申请日：2020-01-14
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Seulji Song , Jonguk Kim , Kyusul Park , Woohyun Park , Jonghyun Paek
Abstract: A semiconductor device includes a plurality of first conductive lines disposed on a substrate, a plurality of second conductive lines intersecting the plurality of first conductive lines, and a plurality of cell structures interposed between the plurality of first conductive lines and the plurality of second conductive lines. At least one among the plurality of cell structures includes a first electrode, a switching element disposed on the first electrode, a second electrode disposed on the switching element, a first metal pattern disposed on the second electrode, a variable resistance pattern interposed between the first metal pattern and at least one among the plurality of second conductive lines, and a first spacer disposed on a sidewall of the variable resistance pattern, a sidewall of the first metal pattern and a sidewall of the second electrode.
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公开(公告)号：US20190019950A1
公开(公告)日：2019-01-17
申请号：US15869892
申请日：2018-01-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sungwon Kim , Sung-Ho Eun , Ilmok Park , Junghoon Park , Seulji Song , Ji-Hyun Jeong
CPC classification number: H01L45/1675 , G11C13/0004 , G11C13/0026 , G11C13/0028 , G11C2213/31 , G11C2213/76 , H01L27/2427 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/122 , H01L45/1233 , H01L45/1273 , H01L45/141 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/1683 , H01L45/1691
Abstract: Variable resistance memory devices and methods of forming the same are provided. The variable resistance memory devices may include a substrate including a cell region and a peripheral region, first conductive lines on the substrate, second conductive lines traversing the first conductive lines, variable resistance structures at intersecting points of the first conductive lines and the second conductive lines, and bottom electrodes between the first conductive lines and the variable resistance structures. The cell region may include a boundary region contacting the peripheral region, and one of the first conductive lines is electrically insulated from one of the variable resistance structures that is on the boundary region and overlaps the one of the first conductive lines,
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公开(公告)号：US20250120116A1
公开(公告)日：2025-04-10
申请号：US18636661
申请日：2024-04-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Suhyun Bang , Seulji Song
Abstract: A vertical semiconductor switching device includes lower and upper conductive patterns, and an active pattern electrically connected between the lower conductive pattern and the upper conductive pattern. The active pattern includes a lower source/drain (S/D) region electrically coupled to the lower conductive pattern, an upper S/D region electrically coupled to the upper conductive pattern, and a channel region having first impurities of a first conductivity type therein, electrically connected to the lower source/drain region and to the upper source/drain region. The channel region includes a lower channel region, an intermediate channel region on the lower channel region, and an upper channel region on the intermediate channel region. A gate electrode is provided on a side surface of the channel region.
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公开(公告)号：US20250063738A1
公开(公告)日：2025-02-20
申请号：US18801958
申请日：2024-08-13
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seulji Song , Hwayeong Lee
IPC: H10B53/30
Abstract: A semiconductor memory device includes an active portion, a pad insulating layer on the active portion and including a pad through hole, a landing pad in the pad through hole and electrically connected to the active portion, and the landing pad including a protrusion protruding towards an upper portion of the pad insulating layer, a lower conductive layer on the pad insulating layer and bordering a side surface of the protrusion of the landing pad, a lower electrode on the landing pad and electrically connected to the landing pad, a ferroelectric layer on the lower conductive layer and bordering the lower electrode, an upper electrode bordering the ferroelectric layer, an electrode insulating layer on the upper electrode, a plate line on the electrode insulating layer and the upper electrode and electrically connected to the upper electrode, wherein the plate line is electrically connected to the lower conductive layer through a through via.
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