公开(公告)号：US20250157921A1

公开(公告)日：2025-05-15

申请号：US18740739

申请日：2024-06-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeewoong Kim ,  Seunghun Lee ,  Kyowook Lee ,  Keunhwi Cho

IPC: H01L23/528 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786 ,  H10B10/00

Abstract: Provided is an integrated circuit device with reduced line margins. The integrated circuit device includes an active area on a substrate, a channel area in the active area, a gate line that extends around the channel area, a plurality of first upper lines that electrically connect the channel area and the gate line to each other, a plurality of first lower lines of a side of the substrate, and a second lower wiring line on a side of the plurality of first lower lines that is opposite the substrate. The plurality of first lower lines includes a jog pattern line and an island pattern line that is spaced apart from the jog pattern line, and the island pattern line is electrically connected to the second lower wiring line by a lower contact.

公开(公告)号：US12209350B2

公开(公告)日：2025-01-28

申请号：US17741572

申请日：2022-05-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seunghun Lee ,  Junhyun Park

IPC: D06F39/08 ,  D06F33/32 ,  D06F34/18 ,  D06F39/04 ,  D06F103/04 ,  D06F103/18 ,  D06F105/06

Abstract: A washing machine according to an aspect of the disclosure includes: a tub; a drum rotatably provided inside the tub; a heater configured to heat water; a circulating pump configured to circulate a part of the water stored in the tub; a water level sensor configured to sense a water level of water in the tub; and a controller configured to control the circulating pump to circulate the part of the water stored in the tub, and control revolutions per minute (rpm) of a motor of the circulating pump based on a water level of the water while the water stored in the tub circulates and the heater is driven.

公开(公告)号：US12063767B2

公开(公告)日：2024-08-13

申请号：US17541790

申请日：2021-12-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myung Gil Kang ,  Seunghun Lee ,  Sangdeok Kwon ,  Keun Hwi Cho ,  Sung Gi Hur

IPC: H01L27/11 ,  H01L29/36 ,  H01L29/423 ,  H01L29/786 ,  H10B10/00

CPC classification number: H10B10/12 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor device includes a first active pattern on a substrate, a pair of first source/drain patterns on the first active pattern and a first channel pattern between the pair of first source/drain patterns, wherein the first channel pattern includes a plurality of semiconductor patterns that are stacked and spaced apart from each other, a first gate electrode on the first channel pattern, a first gate cutting pattern that is adjacent to the first channel pattern and penetrates the first gate electrode, and a first residual pattern between the first gate cutting pattern and the first channel pattern. The first residual pattern covers an outermost sidewall of at least one semiconductor pattern of the plurality of semiconductor patterns of the first channel pattern. The first gate electrode includes, on an upper portion of the first gate electrode, a first extension that vertically overlaps the first residual pattern.

公开(公告)号：US20220068920A1

公开(公告)日：2022-03-03

申请号：US17524128

申请日：2021-11-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungin Choi ,  Dahye Kim ,  Jaemun Kim ,  Jinbum Kim ,  Seunghun Lee

IPC: H01L27/088 ,  H01L29/165 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/02 ,  H01L29/66 ,  H01L21/306 ,  H01L21/762

Abstract: Integrated circuit devices may include a fin-type active area, a semiconductor liner contacting a side wall of the fin-type active area and including a protrusion portion protruding outward from the fin-type active area in the vicinity of an edge of an upper surface of the fin-type active area, and an isolation layer spaced apart from the fin-type active area with the semiconductor liner therebetween. To manufacture the integrated circuit devices, a crystalline semiconductor layer covering the fin-type active area with a first thickness and an amorphous semiconductor layer covering the mask pattern with a second thickness may be formed, an extended crystalline semiconductor layer covering the mask pattern may be formed by crystalizing the amorphous semiconductor layer, and a semiconductor liner including a protrusion portion may be formed from the extended crystalline semiconductor layer and the crystalline semiconductor layer.

公开(公告)号：US11217667B2

公开(公告)日：2022-01-04

申请号：US16806629

申请日：2020-03-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seokhoon Kim ,  Dongmyoung Kim ,  Kanghun Moon ,  Hyunkwan Yu ,  Sanggil Lee ,  Seunghun Lee ,  Sihyung Lee ,  Choeun Lee ,  Edward Namkyu Cho ,  Yang Xu

IPC: H01L29/08 ,  H01L29/78 ,  H01L27/088 ,  H01L29/06

Abstract: A semiconductor device includes a substrate, a fin structure on the substrate, a gate structure on the fin structure, a gate spacer on at least on side surface of the gate structure, and a source/drain structure on the fin structure, wherein a topmost portion of a bottom surface of the gate spacer is lower than a topmost portion of a top surface of the fin structure, and a topmost portion of a top surface of the source/drain structure is lower than the topmost portion of the top surface of the fin structure.

公开(公告)号：US20210313322A1

公开(公告)日：2021-10-07

申请号：US17352763

申请日：2021-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keomyoung Shin ,  Pankwi Park ,  Seunghun Lee

IPC: H01L27/088 ,  H01L29/26 ,  H01L29/78 ,  H01L29/08 ,  H01L29/06

Abstract: An integrated circuit (IC) device includes a fin-type active region extending lengthwise in a first direction, a plurality of nanosheets overlapping each other in a second direction on a fin top surface of the fin-type active region, and a source/drain region on the fin-type active region and facing the plurality of nanosheets in the first direction. The plurality of nanosheets include a first nanosheet, which is closest to the fin top surface of the fin-type active region and has a shortest length in the first direction, from among the plurality of nanosheets. The source/drain region includes a source/drain main region and a first source/drain protruding region protruding from the source/drain main region. The first source/drain protruding region protrudes from the source/drain main region toward the first nanosheet and overlaps portions of the plurality of nanosheets in the second direction.

公开(公告)号：US20250169048A1

公开(公告)日：2025-05-22

申请号：US18671559

申请日：2024-05-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeewoong Kim ,  Kyo-Wook Lee ,  Seunghun Lee ,  Keun Hwi Cho

IPC: H10B10/00 ,  G11C11/412 ,  G11C11/419 ,  H01L23/485 ,  H01L29/417

Abstract: A semiconductor device may include a first lower active contact, a first source/drain pattern on the first lower active contact, a second lower active contact, a second source/drain pattern on the second lower active contact, a lower conductive layer electrically connected to the first and second lower active contacts, a third source/drain pattern and a fourth source/drain pattern between the first and second source/drain patterns, a first upper active contact on the third source/drain pattern, a second upper active contact on the fourth source/drain pattern, and an upper conductive line electrically connected to the first and second upper active contacts. The first to fourth source/drain patterns, the first and second lower active contacts, and the first and second upper active contacts may be disposed between the lower conductive layer and upper conductive line.

公开(公告)号：US12288805B2

公开(公告)日：2025-04-29

申请号：US18667417

申请日：2024-05-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinbum Kim ,  Gyeom Kim ,  Hyojin Kim ,  Haejun Yu ,  Seunghun Lee ,  Kyungin Choi

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/786

Abstract: An integrated circuit device is provided and includes: a fin-type active region extending in a first horizontal direction on a substrate, a channel region on the fin-type active region, a gate line surrounding the channel region on the fin-type active region and extending in a second horizontal direction crossing the first horizontal direction, an insulating spacer covering a sidewall of the gate line, a source/drain region connected to the channel region on the fin-type active region and including a first portion facing the sidewall of the gate line with the insulating spacer therebetween, an air gap between the insulating spacer and the first portion of the source/drain region, and an insulating liner including a portion in contact with the source/drain region and a portion defining a size of the air gap. A method of manufacturing the integrated circuit device is further provided.

公开(公告)号：US12094974B2

公开(公告)日：2024-09-17

申请号：US18307279

申请日：2023-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaemun Kim ,  Dahye Kim ,  Jinbum Kim ,  Gyeom Kim ,  Dohee Kim ,  Dongwoo Kim ,  Seunghun Lee

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/66 ,  H01L29/04

CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L29/41791 ,  H01L29/6681 ,  H01L29/66818 ,  H01L29/045

Abstract: A semiconductor device includes a substrate including a fin-type active region, the fin-type active region extending in a first direction; a plurality of channel layers on the fin-type active region, the plurality of channel layers including an uppermost channel layer, a lowermost channel layer, and an intermediate channel layer isolated from direct contact with each other in a direction perpendicular to an upper surface of the substrate; a gate electrode surrounding the plurality of channel layers and extending in a second direction intersecting the first direction; a gate insulating film between the plurality of channel layers and the gate electrode; and source/drain regions electrically connected to the plurality of channel layers. In a cross section taken in the second direction, the uppermost channel layer has a width greater than a width of the intermediate channel layer.

公开(公告)号：US12034043B2

公开(公告)日：2024-07-09

申请号：US17479424

申请日：2021-09-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinbum Kim ,  Gyeom Kim ,  Hyojin Kim ,  Haejun Yu ,  Seunghun Lee ,  Kyungin Choi

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/0665 ,  H01L29/0653 ,  H01L29/6656 ,  H01L29/78618 ,  H01L29/78696

Abstract: An integrated circuit device includes: a fin-type active region extending in a first horizontal direction on a substrate, a channel region on the fin-type active region, a gate line surrounding the channel region on the fin-type active region and extending in a second horizontal direction crossing the first horizontal direction, an insulating spacer covering a sidewall of the gate line, a source/drain region connected to the channel region on the fin-type active region and including a first portion facing the sidewall of the gate line with the insulating spacer therebetween, an air gap between the insulating spacer and the first portion of the source/drain region, and an insulating liner including a portion in contact with the source/drain region and a portion defining a size of the air gap.