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    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    1.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20250107075A1

    公开(公告)日：2025-03-27

    申请号：US18809859

    申请日：2024-08-20

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyunghwan KIM ,  Joongchan SHIN ,  Hyungeun CHOI ,  Taegyu KANG ,  Keunui KIM ,  Bowon YOO

    IPC: H10B12/00

    Abstract: A semiconductor device includes a substrate including a cell array area and an interface area, bit lines on the cell array area and extending in a first horizontal direction, back gate lines on the bit lines and extending in a second direction, insulating blocks on the interface area and each overlapping the back gate lines in the second direction, word lines among which each pair of two adjacent word lines are on both sides of a corresponding back gate line, respectively, and extending on a sidewall of a corresponding insulating block, active semiconductor layers each between a corresponding back gate line and a corresponding word line on the cell array area and having one end electrically connected to a corresponding bit line, and a word line contact on the interface area and on a corresponding word line and a corresponding insulating block adjacent thereto.

    SEMICONDUCTOR MEMORY DEVICES
    3.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES 有权

    公开(公告)号：US20220085023A1

    公开(公告)日：2022-03-17

    申请号：US17471778

    申请日：2021-09-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seokho SHIN ,  Taegyu KANG ,  Byeungmoo KANG ,  Joongchan SHIN

    IPC: H01L27/108

    Abstract: A semiconductor memory device including a substrate; a semiconductor pattern extending in a first horizontal direction on the substrate; bit lines extending in a second horizontal direction on the substrate perpendicular to the first horizontal direction, the bit lines being at a first end of the semiconductor pattern; word lines extending in a vertical direction on the substrate at a side of the semiconductor pattern; a capacitor structure on a second end of the semiconductor pattern opposite to the first end in the first horizontal direction, the capacitor structure including a lower electrode connected to the semiconductor pattern, an upper electrode spaced apart from the lower electrode, and a capacitor dielectric layer between the lower electrode and the upper electrode; and a capacitor contact layer between the second end of the semiconductor pattern and the lower electrode and including a pair of convex surfaces in contact with the semiconductor pattern.

    SEMICONDUCTOR DEVICES
    4.
    发明申请
    SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20250107071A1

    公开(公告)日：2025-03-27

    申请号：US18671624

    申请日：2024-05-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Taegyu KANG ,  Keunui KIM ,  Seokhan PARK ,  Joongchan SHIN ,  Gyuhwan OH ,  Bowon YOO ,  Kiseok LEE ,  Sangho LEE ,  Eunsuk JANG ,  Moonyoung JEONG

    IPC: H10B12/00

    Abstract: A semiconductor device comprising: a substrate; bit lines on the substrate; word lines on the bit lines, wherein the word lines are spaced apart from each other in a first direction; activation patterns between the word lines; a back gate electrode between the activation patterns, wherein the back gate electrode extends in a second direction; and a first gate separation pattern between the word lines in the first direction, wherein a portion of the word lines is a space between the activation patterns in the second direction and the word lines extend around the activation patterns, wherein the word lines and the first gate separation pattern each include a first surface facing the bit lines and a second surface opposite to the first surface in a third direction, wherein the first gate separation pattern is closer than the word lines to the bit lines in the third direction.

    SEMICONDUCTOR MEMORY DEVICE
    5.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20240147707A1

    公开(公告)日：2024-05-02

    申请号：US18242817

    申请日：2023-09-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Taegyu KANG ,  Taehyuk KIM ,  Seok-Ho SHIN ,  Keunnam KIM ,  Seokhan PARK ,  Joongchan SHIN ,  Kiseok LEE

    IPC: H10B12/00 ,  H01L23/522

    CPC classification number: H10B12/50 ,  H01L23/5225 ,  H10B12/09 ,  H10B12/315 ,  H10B12/482

    Abstract: A semiconductor memory device may include a substrate including a cell array region and a peripheral circuit region, an active pattern on the cell array region of the substrate, a peripheral active pattern on the peripheral circuit region of the substrate, a peripheral gate electrode disposed on a top surface of the peripheral active pattern, a first interlayer insulating pattern provided on the cell array region to cover a top surface of the active pattern, a first etch stop layer covering the first interlayer insulating pattern and the peripheral gate electrode with a uniform thickness, and a second interlayer insulating pattern disposed on the first etch stop layer and in the peripheral circuit region. In the cell array region, the second interlayer insulating pattern may have a top surface, which is located at substantially the same level as a top surface of the first etch stop layer.

    METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY DEVICES
    6.
    发明公开
    METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY DEVICES 审中-公开

    公开(公告)号：US20230276614A1

    公开(公告)日：2023-08-31

    申请号：US18144958

    申请日：2023-05-09

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seokho SHIN ,  Taegyu KANG ,  Byeungmoo KANG ,  Joongchan SHIN

    IPC: H10B12/00

    CPC classification number: H10B12/30 ,  H10B12/03 ,  H10B12/05

    Abstract: A semiconductor memory device including a substrate; a semiconductor pattern extending in a first horizontal direction on the substrate; bit lines extending in a second horizontal direction on the substrate perpendicular to the first horizontal direction, the bit lines being at a first end of the semiconductor pattern; word lines extending in a vertical direction on the substrate at a side of the semiconductor pattern; a capacitor structure on a second end of the semiconductor pattern opposite to the first end in the first horizontal direction, the capacitor structure including a lower electrode connected to the semiconductor pattern, an upper electrode spaced apart from the lower electrode, and a capacitor dielectric layer between the lower electrode and the upper electrode; and a capacitor contact layer between the second end of the semiconductor pattern and the lower electrode and including a pair of convex surfaces in contact with the semiconductor pattern.

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