Encoding and decoding of data using generalized LDPC codes

    公开(公告)号:US12143123B2

    公开(公告)日:2024-11-12

    申请号:US18358660

    申请日:2023-07-25

    Abstract: A method of correcting data stored in a memory device includes: applying an iterative decoder to the data; determining a total number of rows in first data the decoder attempted to correct; estimating first visible error rows among the total number that continue to have an error after the attempt; estimating residual error rows among the total number that no longer have an error after the attempt; determining second visible error rows in second data of the decoder that continue to have an error by permuting indices of the residual error rows according to a permutation; and correcting the first data using the first visible error rows.

    Non-volatile memory device and programming method using fewer verification voltages than programmable data states
    5.
    发明授权
    Non-volatile memory device and programming method using fewer verification voltages than programmable data states 有权
    非易失性存储器件和使用比可编程数据状态更少的验证电压的编程方法

    公开(公告)号:US09202576B2

    公开(公告)日:2015-12-01

    申请号:US14211077

    申请日:2014-03-14

    CPC classification number: G11C16/10 G11C11/5628 G11C16/3459

    Abstract: A method of programming a non-volatile memory device includes; defining a set of verification voltages, setting a maximum verification voltage among verification voltages that are less than or equal to a first target programming voltage to be a target verification voltage, calculating a number of extra pulses based on the target verification voltage and the first target programming voltage, verifying whether a threshold voltage of the memory cell is equal to or greater than the target verification voltage by applying an incremental step pulse program (ISPP) pulse to the memory cell and then applying at least one verification voltage in the set of verification voltages to the memory cell, and further applying the ISPP pulse to the memory cell a number of times equal to the number of extra pulses when the threshold voltage is verified to be equal to or greater than the target verification voltage.

    Abstract translation: 非易失性存储器件的编程方法包括: 定义一组验证电压,将小于或等于第一目标编程电压的验证电压之间的最大验证电压设置为目标验证电压,基于目标验证电压和第一目标计算额外脉冲数 编程电压,通过向存储单元施加增量步进脉冲程序(ISPP)脉冲,然后在验证集合中施加至少一个验证电压来验证存储器单元的阈值电压是否等于或大于目标验证电压 并且当阈值电压被验证为等于或大于目标验证电压时,进一步将ISPP脉冲施加到存储器单元等于额外脉冲数的次数。

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