公开(公告)号：US12243593B2

公开(公告)日：2025-03-04

申请号：US17685613

申请日：2022-03-03

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Deepanshu Dutta ,  Ohwon Kwon ,  James Kai ,  Yuki Mizutani

IPC: G11C16/24 ,  G11C16/04 ,  G11C16/26 ,  G11C16/08

Abstract: The memory device includes a chip with circuitry, a plurality of memory blocks, and a plurality of bit lines. The memory blocks include an array of memory cells, and the circuitry either overlies or underlies the array of memory cells. The bit lines are divided into two portions that are electrically connected with one another via at least one transistor so that at least one portion of each bit line can be charged independently of the other portion of the same bit line.

公开(公告)号：US11990185B2

公开(公告)日：2024-05-21

申请号：US17888063

申请日：2022-08-15

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  YenLung Li ,  James Kai

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16

CPC classification number: G11C16/08 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16

Abstract: Technology is disclosed herein reconfiguring word lines as either data word lines or dummy word lines. In a sub-block mode reconfigurable word lines are used as dummy word lines that provide electrical isolation between data word lines in a block. The block may be divided into an upper tier, a middle tier, and a lower tier, with the reconfigurable word lines within the middle tier. In a full-block mode the reconfigurable group of the word lines are used as data word lines. Because the reconfigurable word lines are used as data word lines in the full-block mode storage capacity is greater in the full-block mode than in the sub-block mode. Moreover, because the sub-blocks are smaller in size but greater in number than the full-blocks, the memory system may be provisioned with fewer blocks and still meet user storage requirements in both the full-block mode and the sub-block mode.

公开(公告)号：US20230163116A1

公开(公告)日：2023-05-25

申请号：US18100152

申请日：2023-01-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Johann Alsmeier ,  James Kai ,  Koichi Matsuno

IPC: H01L25/18 ,  H01L25/00 ,  H01L25/065 ,  H10B43/40

CPC classification number: H01L25/18 ,  H01L25/50 ,  H01L25/0657 ,  H10B43/40 ,  H01L2225/06541 ,  H10B41/27

Abstract: A bonded assembly includes a first three-dimensional memory die containing a first alternating stack of first insulating layers and first electrically conductive layers and first memory structures located in the first alternating stack, a second three-dimensional memory die bonded to the first three-dimensional memory die, and containing a second alternating stack of second insulating layers and second electrically conductive layers, and second memory structures located in the second alternating stack. The first electrically conductive layers have different lateral extents along the first horizontal direction that decrease with a respective vertical distance from driver circuit devices, and the second electrically conductive layers have different lateral extents along the first horizontal direction that increase with the respective vertical distance from the driver circuit devices.

公开(公告)号：US11037943B2

公开(公告)日：2021-06-15

申请号：US16406283

申请日：2019-05-08

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Muneyuki Imai ,  James Kai

IPC: H01L27/11556 ,  H01L27/11582 ,  G11C16/04 ,  H01L29/06 ,  H01L21/28

Abstract: An array of memory stack structures extends through an alternating stack of insulating layers and electrically conductive layers. The drain-select-level assemblies may be provided by forming drain-select-level openings through a drain-select-level sacrificial material layer, and by forming a combination of a cylindrical electrode portion and a first gate dielectric mayin each first drain-select-level opening while forming a second gate dielectric directly on a sidewall of each second drain-select-level opening in a second subset of the drain-select-level openings. A strip electrode portion is formed by replacing the drain-select-level sacrificial material layer with a conductive material. Structures filling the second subset of the drain-select-level openings may be used as dummy structures at a periphery of an array. The dummy structures are free of gate electrodes and thus prevents a leakage current therethrough.

公开(公告)号：US10950626B2

公开(公告)日：2021-03-16

申请号：US16539124

申请日：2019-08-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： James Kai ,  Johann Alsmeier ,  Murshed Chowdhury ,  Raiden Matsuno

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/792 ,  H01L29/732 ,  H01L27/11582 ,  G11C5/06 ,  H01L27/11565 ,  H01L27/1157

Abstract: A three-dimensional memory device includes an alternating stack of source layers and drain layers located over a substrate, gate electrodes vertically extending through each of the source layers and the drain layers of the alternating stack, memory films laterally surrounding a respective one of the gate electrodes, and semiconductor channels laterally surrounding a respective one of the memory films and connected to a respective vertically neighboring pair of a source layer and a drain layer. An array of memory openings can vertically extend through the alternating stack, and each of the gate electrodes can be located within a respective one of the memory openings.

公开(公告)号：US10943917B2

公开(公告)日：2021-03-09

申请号：US16388054

申请日：2019-04-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takaaki Iwai ,  Makoto Koto ,  Sayako Nagamine ,  Ching-Huang Lu ,  Wei Zhao ,  Yanli Zhang ,  James Kai

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L21/762 ,  H01L27/11565 ,  H01L27/11556

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory pillar structures extending through the alternating stack. Each of the memory pillar structures includes a respective memory film and a respective vertical semiconductor channel. Dielectric cores contact an inner sidewall of a respective one of the vertical semiconductor channels. A drain-select-level isolation structure laterally extends along a first horizontal direction and contacts straight sidewalls of the dielectric cores at a respective two-dimensional flat interface. The memory pillar structures may be formed on-pitch as a two-dimensional periodic array, and themay drain-select-level isolation structure may cut through upper portions of the memory pillar structures to minimize areas occupied by the drain-select-level isolation structure.

公开(公告)号：US10748894B2

公开(公告)日：2020-08-18

申请号：US16251954

申请日：2019-01-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Murshed Chowdhury ,  Kwang-Ho Kim ,  James Kai ,  Johann Alsmeier

IPC: G11C15/00 ,  H01L27/06 ,  H01L27/108 ,  H01L27/11529 ,  G11C5/02 ,  H01L23/48 ,  H01L23/00 ,  H01L27/1157

Abstract: A memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures extending through the alternating stack, source regions located on, or in, the substrate, and at least one memory-side bonding pad electrically connected to the source regions. A logic die includes a power supply circuit configured to generate a supply voltage for the source regions, and at least one logic-side bonding pad electrically connected to the power supply circuit through a network of logic-side metal interconnect structures. The memory die is bonded to the logic die. The network of logic-side metal interconnect structures distributes source power from the power supply circuit over an entire area of the memory stack structures and transmits the source power to the memory die through bonded pairs of memory-side bonding pads and logic-side bonding pads.

公开(公告)号：US10403639B2

公开(公告)日：2019-09-03

申请号：US15818146

申请日：2017-11-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takashi Orimoto ,  James Kai ,  Sayako Nagamine ,  Takaaki Iwai ,  Shigeyuki Sugihara ,  Shuji Minagawa

IPC: H01L21/02 ,  H01L21/28 ,  H01L29/06 ,  H01L29/51 ,  H01L29/66 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582

Abstract: An array of memory stack structures extends through an alternating stack of insulating layers and electrically conductive layers over a substrate. An array of drain select level assemblies including cylindrical electrode portions is formed over the alternating stack with the same periodicity as the array of memory stack structures. A drain select level isolation strip including dielectric materials can be formed between a neighboring pair of drain select level assemblies employing the drain select level assemblies as a self-aligning template. Alternatively, cylindrical electrode portions can be formed around an upper portion of each memory stack structure. Strip electrode portions are formed on the cylindrical electrode portions after formation of the drain select level isolation strip.

公开(公告)号：US10355015B2

公开(公告)日：2019-07-16

申请号：US15948737

申请日：2018-04-09

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yanli Zhang ,  James Kai ,  Johann Alsmeier

IPC: G11C16/10 ,  G11C16/26 ,  H01L27/11582 ,  H01L27/1157 ,  G11C16/24 ,  G11C16/04 ,  H01L29/792 ,  G11C16/08 ,  H01L27/11575

Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers. Vertical NAND strings are formed through the alternating stack, each of which includes a drain region, memory cell charge storage transistors, and a pair of drain select transistors in a series connection. A common bit line is electrically connected to drain regions of two vertical NAND strings. The drain select transistors of the two vertical NAND strings are configured such that drain select transistors sharing a first common drain select gate electrode provide a higher threshold voltage for one of the two vertical NAND strings, and drain select transistors sharing a second common drain select gate electrode provide a higher threshold voltage for the other of the two vertical NAND strings. The different threshold voltages can be provided by a combination of a masked ion implantation and selective charge injection.

公开(公告)号：US10121794B2

公开(公告)日：2018-11-06

申请号：US15279959

申请日：2016-09-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Marika Gunji-Yoneoka ,  Atsushi Suyama ,  Jayavel Pachamuthu ,  Tsuyoshi Hada ,  Daewung Kang ,  Murshed Chowdhury ,  James Kai ,  Hiro Kinoshita ,  Tomoyuki Obu ,  Luckshitha Suriyasena Liyanage

IPC: H01L27/115 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/1157

Abstract: An alternating stack of insulating layers and spacer material layers is formed over a semiconductor substrate. Memory openings are formed through the alternating stack. An optional silicon-containing epitaxial pedestal and a memory film are formed in each memory opening. After forming an opening through a bottom portion of the memory film within each memory opening, a germanium-containing semiconductor layer and a dielectric layer is formed in each memory opening. Employing the memory film and the dielectric layer as a crucible, a liquid phase epitaxy anneal is performed to convert the germanium-containing semiconductor layer into a germanium-containing epitaxial channel layer. A dielectric core and a drain region can be formed over the dielectric layer. The germanium-containing epitaxial channel layer is single crystalline, and can provide a higher charge carrier mobility than a polysilicon channel.