公开(公告)号：US20080036081A1

公开(公告)日：2008-02-14

申请号：US11875713

申请日：2007-10-19

申请人： Se-Young JEONG ,  Sung-Min SIM ,  Soon-Bum KIM ,  In-Young LEE ,  Young-Hee SONG

发明人： Se-Young JEONG ,  Sung-Min SIM ,  Soon-Bum KIM ,  In-Young LEE ,  Young-Hee SONG

IPC分类号： H01L23/48

CPC分类号： H01L24/05 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05018 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/05552

摘要： An interconnection structure includes an integrated circuit (IC) chip having internal circuitry and a terminal to electrically connect the internal circuitry to an external circuit, a passivation layer disposed on a top surface of the IC chip, the passivation layer configured to protect the internal circuitry and to expose the terminal, an input/output (I/O) pad, where the I/O pad includes a first portion in contact with the terminal and a second portion that extends over the passivation layer, and an electroless plating layer disposed on the I/O pad.

摘要翻译： 互连结构包括具有内部电路的集成电路（IC）芯片和用于将内部电路电连接到外部电路的端子，设置在IC芯片的顶表面上的钝化层，该钝化层被配置为保护内部电路 以及使所述终端暴露于所述I / O焊盘包括与所述端子接触的第一部分和在所述钝化层上延伸的第二部分的输入/输出（I / O）焊盘，以及设置在所述钝化层上的无电镀层 I / O板。

公开(公告)号：US20070164431A1

公开(公告)日：2007-07-19

申请号：US11549933

申请日：2006-10-16

申请人： In Young LEE ,  Hyun-Soo CHUNG ,  Dong-Ho LEE ,  Sung-Min SIM ,  Dong-Soo SEO ,  Seung-Kwan RYU ,  Myeong-Soon PARK

发明人： In Young LEE ,  Hyun-Soo CHUNG ,  Dong-Ho LEE ,  Sung-Min SIM ,  Dong-Soo SEO ,  Seung-Kwan RYU ,  Myeong-Soon PARK

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H01L23/3114 ,  H01L23/5222 ,  H01L23/525 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/0231 ,  H01L2224/02313 ,  H01L2224/0236 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2924/00

摘要： A wafer level chip scale package capable of reducing parasitic capacitances between a rerouting and the metal wiring of a wafer, and a method for manufacturing the same are provided. An embodiment of the wafer level chip scale package includes a wafer arranged with a plurality of bonding pads and an insulating member formed on the wafer so that the bonding pads are exposed. A rerouting is further formed on the insulating member in contact with the exposed bonding pads and an external connecting terminal is electrically connected to a portion of the rerouting. Here, the insulating member overlapping the rerouting is provided with a plurality of spaces in which air is trapped.

摘要翻译： 提供能够降低重新布线和晶片的金属布线之间的寄生电容的晶片级芯片级封装及其制造方法。 晶片级芯片级封装的实施例包括具有多个接合焊盘的晶片和形成在晶片上的绝缘部件，使得焊盘露出。 在与暴露的接合焊盘接触的绝缘构件上进一步形成再路由，并且外部连接端子电连接到重新布线的一部分。 这里，与重新路由重叠的绝缘构件设置有空气被捕获的多个空间。

公开(公告)号：US20090020878A1

公开(公告)日：2009-01-22

申请号：US12014600

申请日：2008-01-15

申请人： Seung-Kwan RYU ,  Hee-Kook CHOI ,  Sung-Min SIM ,  Dong-Hyeon JANG

发明人： Seung-Kwan RYU ,  Hee-Kook CHOI ,  Sung-Min SIM ,  Dong-Hyeon JANG

IPC分类号： H01L21/768 ,  H01L23/52

CPC分类号： H01L23/3114 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01021 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01059 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/30105

摘要： A semiconductor package is provided. The semiconductor package includes a semiconductor device having a bonding pad and an interlayer insulating layer disposed on the semiconductor device. The interlayer insulating layer has an opening which exposes the bonding pad and has at least one cavity therein. A redistributed interconnection is disposed on the interlayer insulating layer and electrically connected to the exposed bonding pad. The redistributed interconnection is disposed over the cavity. A method of fabricating the semiconductor package is also provided.

摘要翻译： 提供半导体封装。 半导体封装包括具有接合焊盘和设置在半导体器件上的层间绝缘层的半导体器件。 层间绝缘层具有露出接合焊盘并且在其中具有至少一个空腔的开口。 重新分布的互连布置在层间绝缘层上并电连接到暴露的焊盘。 再分布的互连设置在空腔上。 还提供了制造半导体封装的方法。