公开(公告)号：US09293217B2

公开(公告)日：2016-03-22

申请号：US14214097

申请日：2014-03-14

Applicant: Silicon Storage Technology, Inc.

Inventor： Xian Liu ,  James Cheng ,  Dmitry Bavinov ,  Alexander Kotov ,  Jong-Won Yoo

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/12 ,  G11C11/56 ,  G11C16/10

Abstract: A non-volatile memory device and method for programming cells using repeated pulses of program voltages, with interleaved read operations to determine the level of read current, until the desired programming state is achieved. Each successive program pulse has one or more program voltages increased by a step value relative to the previous pulse. For a single level cell type, each cell is individually removed from the programming pulses after reaching a first read current threshold, and the step value is increased for one or more kicker pulses thereafter. For a multi-level cell type, the step value drops after one of the cells reaches a first read current threshold, some cells are individually removed from the programming pulses after reaching a second read current threshold while others are individually removed from the programming pulses after reaching a third read current threshold.

公开(公告)号：US20160336072A1

公开(公告)日：2016-11-17

申请号：US15084955

申请日：2016-03-30

Applicant: Silicon Storage Technology, Inc.

Inventor： Xiaozhou Qian ,  Viktor Markov ,  Jong-Won Yoo ,  Xiao Yan Pi ,  Alexander Kotov

IPC: G11C16/12 ,  G11C16/04

CPC classification number: G11C16/12 ,  G11C16/0425 ,  G11C16/10

Abstract: The disclosed embodiments comprise a flash memory device and a method of programming the device in a way that reduces degradation of the device compared to prior art methods.

Abstract translation: 所公开的实施例包括闪存器件和以与现有技术方法相比降低器件劣化的方式对器件进行编程的方法。

公开(公告)号：US20150035040A1

公开(公告)日：2015-02-05

申请号：US13958483

申请日：2013-08-02

Applicant: Silicon Storage Technology, Inc.

Inventor： Jong-Won Yoo ,  Alexander Kotov ,  Yuri Tkachev ,  Chien-Sheng Su

IPC: H01L29/788 ,  H01L29/66

CPC classification number: H01L29/788 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7883

Abstract: A non-volatile memory cell includes a substrate of a first conductivity type with first and second spaced apart regions of a second conductivity type, forming a channel region therebetween. A select gate is insulated from and disposed over a first portion of the channel region which is adjacent to the first region. A floating gate is insulated from and disposed over a second portion of the channel region which is adjacent the second region. Metal material is formed in contact with the floating gate. A control gate is insulated from and disposed over the floating gate. An erase gate includes a first portion insulated from and disposed over the second region and is insulated from and disposed laterally adjacent to the floating gate, and a second portion insulated from and laterally adjacent to the control gate and partially extends over and vertically overlaps the floating gate.

Abstract translation: 非易失性存储单元包括具有第一和第二间隔开的第二导电类型的第一导电类型的衬底，在它们之间形成沟道区。 选择栅极与与第一区域相邻的沟道区域的第一部分绝缘并布置在其上。 浮动栅极与邻近第二区域的沟道区域的第二部分绝缘并布置在其上。 金属材料形成为与浮动栅极接触。 控制栅极与浮动栅极绝缘并设置在浮动栅极上。 擦除栅极包括与第二区域绝缘并且布置在第二区域上的第一部分，并且与浮动栅极绝缘并横向邻近设置，以及与控制栅极绝缘并横向邻近控制栅极的第二部分，并且部分地延伸越过浮动 门。

公开(公告)号：US10079061B2

公开(公告)日：2018-09-18

申请号：US15084955

申请日：2016-03-30

Applicant: Silicon Storage Technology, Inc.

Inventor： Xiaozhou Qian ,  Viktor Markov ,  Jong-Won Yoo ,  Xiao Yan Pi ,  Alexander Kotov

IPC: G11C11/34 ,  G11C16/12 ,  G11C16/04 ,  G11C16/10

CPC classification number: G11C16/12 ,  G11C16/0425 ,  G11C16/10

Abstract: The disclosed embodiments comprise a flash memory device and a method of programming the device in a way that reduces degradation of the device compared to prior art methods.

公开(公告)号：US09431126B2

公开(公告)日：2016-08-30

申请号：US14214097

申请日：2014-03-14

Applicant: Silicon Storage Technology, Inc.

Inventor： Xian Liu ,  James Cheng ,  Dmitry Bavinov ,  Alexander Kotov ,  Jong-Won Yoo

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/12 ,  G11C11/56 ,  G11C16/10

CPC classification number: G11C16/3486 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0441 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3459

Abstract: A non-volatile memory device and method for programming cells using repeated pulses of program voltages, with interleaved read operations to determine the level of read current, until the desired programming state is achieved. Each successive program pulse has one or more program voltages increased by a step value relative to the previous pulse. For a single level cell type, each cell is individually removed from the programming pulses after reaching a first read current threshold, and the step value is increased for one or more kicker pulses thereafter. For a multi-level cell type, the step value drops after one of the cells reaches a first read current threshold, some cells are individually removed from the programming pulses after reaching a second read current threshold while others are individually removed from the programming pulses after reaching a third read current threshold.

Abstract translation: 一种用于使用编程电压的重复脉冲编程单元的非易失性存储器件和方法，具有交错读取操作以确定读取电流的电平，直到达到期望的编程状态。 每个连续的编程脉冲具有相对于先前脉冲增加阶跃值的一个或多个编程电压。 对于单级单元类型，在达到第一读取电流阈值之后，每个单元从编程脉冲中单独地移除，并且此后的一个或多个猝发脉冲的步长值增加。 对于多级单元类型，步长值在其中一个单元达到第一读取电流阈值后下降，一些单元在达到第二读取电流阈值之后单独地从编程脉冲中移除，而其他单元在编程脉冲之后被单独从编程脉冲中移除 达到第三个读取电流阈值。

公开(公告)号：US09275748B2

公开(公告)日：2016-03-01

申请号：US14190010

申请日：2014-02-25

Applicant: Silicon Storage Technology, Inc.

Inventor： Nhan Do ,  Steven Malcolm Lemke ,  Jinho Kim ,  Jong-Won Yoo ,  Alexander Kotov ,  Yuri Tkachev

IPC: G11C16/26 ,  G11C16/14 ,  G11C16/04 ,  H01L21/28 ,  H01L29/788 ,  H01L27/115 ,  H01L29/423

CPC classification number: G11C16/26 ,  G11C16/0408 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/14 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/7881

Abstract: A method of reading a memory device having rows and columns of memory cells formed on a substrate, where each memory cell includes spaced apart first and second regions with a channel region therebetween, a floating gate disposed over a first portion of the channel region, a select gate disposed over a second portion of the channel region, a control gate disposed over the floating gate, and an erase gate disposed over the first region. The method includes placing a small positive voltage on the unselected source lines, and/or a small negative voltage on the unselected word lines, during the read operation to suppress sub-threshold leakage and thereby improve read performance.

Abstract translation: 一种读取存储器件的方法，所述存储器件具有形成在衬底上的存储器单元的行和列，其中每个存储器单元包括间隔开的第一和第二区域，其间具有通道区域;布置在沟道区域的第一部分上的浮置栅极， 设置在通道区域的第二部分上的选择栅极，设置在浮置栅极上的控制栅极以及设置在第一区域上的擦除栅极。 该方法包括在读取操作期间在未选择的源极线上放置小的正电压和/或在未选择的字线上施加小的负电压以抑制亚阈值泄漏，从而提高读取性能。

公开(公告)号：US09123822B2

公开(公告)日：2015-09-01

申请号：US13958483

申请日：2013-08-02

Applicant: Silicon Storage Technology, Inc.

Inventor： Jong-Won Yoo ,  Alexander Kotov ,  Yuri Tkachev ,  Chien-Sheng Su

IPC: H01L29/788 ,  H01L29/66 ,  H01L21/28 ,  H01L29/423 ,  H01L27/115

CPC classification number: H01L29/788 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7883

Abstract: A non-volatile memory cell includes a substrate of a first conductivity type with first and second spaced apart regions of a second conductivity type, forming a channel region therebetween. A select gate is insulated from and disposed over a first portion of the channel region which is adjacent to the first region. A floating gate is insulated from and disposed over a second portion of the channel region which is adjacent the second region. Metal material is formed in contact with the floating gate. A control gate is insulated from and disposed over the floating gate. An erase gate includes a first portion insulated from and disposed over the second region and is insulated from and disposed laterally adjacent to the floating gate, and a second portion insulated from and laterally adjacent to the control gate and partially extends over and vertically overlaps the floating gate.

Abstract translation: 非易失性存储单元包括具有第一和第二间隔开的第二导电类型的第一导电类型的衬底，在它们之间形成沟道区。 选择栅极与与第一区域相邻的沟道区域的第一部分绝缘并布置在其上。 浮动栅极与邻近第二区域的沟道区域的第二部分绝缘并布置在其上。 金属材料形成为与浮动栅极接触。 控制栅极与浮动栅极绝缘并设置在浮动栅极上。 擦除栅极包括与第二区域绝缘并且布置在第二区域上的第一部分，并且与浮动栅极绝缘并横向邻近设置，以及与控制栅极绝缘并横向邻近控制栅极的第二部分，并且部分地延伸越过浮动 门。

公开(公告)号：US09123431B2

公开(公告)日：2015-09-01

申请号：US14214097

申请日：2014-03-14

Applicant: Silicon Storage Technology, Inc.

Inventor： Xian Liu ,  James Cheng ,  Dmitry Bavinov ,  Alexander Kotov ,  Jong-Won Yoo

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/12 ,  G11C11/56 ,  G11C16/10

Abstract: A non-volatile memory device and method for programming cells using repeated pulses of program voltages, with interleaved read operations to determine the level of read current, until the desired programming state is achieved. Each successive program pulse has one or more program voltages increased by a step value relative to the previous pulse. For a single level cell type, each cell is individually removed from the programming pulses after reaching a first read current threshold, and the step value is increased for one or more kicker pulses thereafter. For a multi-level cell type, the step value drops after one of the cells reaches a first read current threshold, some cells are individually removed from the programming pulses after reaching a second read current threshold while others are individually removed from the programming pulses after reaching a third read current threshold.

公开(公告)号：US20140269062A1

公开(公告)日：2014-09-18

申请号：US14190010

申请日：2014-02-25

Applicant: Silicon Storage Technology, Inc.

Inventor： Nhan Do ,  Steven Malcolm Lemke ,  Jinho Kim ,  Jong-Won Yoo ,  Alexander Kotov ,  Yuri Tkachev

IPC: G11C16/26 ,  G11C16/14 ,  G11C16/04

CPC classification number: G11C16/26 ,  G11C16/0408 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/14 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/7881

Abstract: A method of reading a memory device having rows and columns of memory cells formed on a substrate, where each memory cell includes spaced apart first and second regions with a channel region therebetween, a floating gate disposed over a first portion of the channel region, a select gate disposed over a second portion of the channel region, a control gate disposed over the floating gate, and an erase gate disposed over the first region. The method includes placing a small positive voltage on the unselected source lines, and/or a small negative voltage on the unselected word lines, during the read operation to suppress sub-threshold leakage and thereby improve read performance.

Abstract translation: 一种读取存储器件的方法，所述存储器件具有形成在衬底上的存储器单元的行和列，其中每个存储器单元包括间隔开的第一和第二区域，其间具有通道区域;布置在沟道区域的第一部分上的浮置栅极， 设置在通道区域的第二部分上的选择栅极，设置在浮置栅极上的控制栅极以及设置在第一区域上的擦除栅极。 该方法包括在读取操作期间在未选择的源极线上放置小的正电压和/或在未选择的字线上施加小的负电压以抑制亚阈值泄漏，从而提高读取性能。

公开(公告)号：US20140269058A1

公开(公告)日：2014-09-18

申请号：US14214097

申请日：2014-03-14

Applicant: Silicon Storage Technology, Inc.

Inventor： Xian Liu ,  James Cheng ,  Dmitry Bavinov ,  Alexander Kotov ,  Jong-Won Yoo

IPC: G11C16/34 ,  G11C16/12

CPC classification number: G11C16/3486 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0441 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3459

Abstract: A non-volatile memory device and method for programming cells using repeated pulses of program voltages, with interleaved read operations to determine the level of read current, until the desired programming state is achieved. Each successive program pulse has one or more program voltages increased by a step value relative to the previous pulse. For a single level cell type, each cell is individually removed from the programming pulses after reaching a first read current threshold, and the step value is increased for one or more kicker pulses thereafter. For a multi-level cell type, the step value drops after one of the cells reaches a first read current threshold, some cells are individually removed from the programming pulses after reaching a second read current threshold while others are individually removed from the programming pulses after reaching a third read current threshold.

Abstract translation: 一种用于使用编程电压的重复脉冲编程单元的非易失性存储器件和方法，具有交错读取操作以确定读取电流的电平，直到达到期望的编程状态。 每个连续的编程脉冲具有相对于先前脉冲增加阶跃值的一个或多个编程电压。 对于单级单元类型，在达到第一读取电流阈值之后，每个单元从编程脉冲中单独地移除，并且此后的一个或多个猝发脉冲的步长值增加。 对于多级单元类型，步长值在其中一个单元达到第一读取电流阈值后下降，一些单元在达到第二读取电流阈值之后单独地从编程脉冲中移除，而其他单元在编程脉冲之后被单独从编程脉冲中移除 达到第三个读取电流阈值。