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    HETEROSTRUCTURE AND METHOD OF FABRICATION
    2.
    发明申请
    HETEROSTRUCTURE AND METHOD OF FABRICATION 审中-公开

    公开(公告)号：US20200280298A1

    公开(公告)日：2020-09-03

    申请号：US16877309

    申请日：2020-05-18

    Applicant: Soitec

    Inventor： Arnaud Castex ,  Daniel Delprat ,  Bernard Aspar ,  Ionut Radu

    IPC: H03H9/02 ,  H01L41/312 ,  H01L41/08 ,  H01L41/313 ,  H03H3/10

    Abstract: The present invention relates to a heterostructure, in particular, a piezoelectric structure, comprising a cover layer, in particular, a layer of piezoelectric material, the material of the cover layer having a first coefficient of thermal expansion, assembled to a support substrate, the support substrate having a second coefficient of thermal expansion substantially different from the first coefficient of thermal expansion, at an interface wherein the cover layer comprises at least a recess extending from the interface into the cover layer, and its method of fabrication.

    Method for trimming a structure obtained by the assembly of two plates
    3.
    发明授权
    Method for trimming a structure obtained by the assembly of two plates 有权
    用于修整通过组装两个板获得的结构的方法

    公开(公告)号：US08628674B2

    公开(公告)日：2014-01-14

    申请号：US13682009

    申请日：2012-11-20

    Applicant: SOITEC ,  Commissariat A l'Energie Atomique et Aux Energies Alternatives

    Inventor： Marc Zussy ,  Bernard Aspar ,  Chrystelle Lagahe-Blanchard ,  Hubert Moriceau

    IPC: H01L21/02

    CPC classification number: H01L21/02008 ,  H01L21/76251 ,  H01L21/76254 ,  Y10T156/10

    Abstract: A method for trimming a structure obtained by bonding a first wafer to a second waver on contact faces and thinning the first waver, wherein at least either the first wafer or the second wafer is chamfered and thus exposes the edge of the contact face of the first wafer, wherein the trimming concerns the first wafer. The method includes a) selecting the second wafer from among wafers with a resistance to a chemical etching planned in b) that is sufficient with respect to the first wafer to allow b) to be carried out; b) after bonding the first wafer to the second wafer, chemical etching the edge of the first wafer to form in the first wafer a pedestal resting entirely on the contact face of the second wafer and supporting the remaining of the first wafer; and c) thinning the first wafer until the pedestal is reached and attacked, to provide a thinned part of the first wafer.

    Abstract translation: 一种用于修整通过将第一晶片接合在接触面上的第二摆动件并使第一摇摆器变薄而获得的结构的方法，其中至少第一晶片或第二晶片被倒角，从而使第一晶片或第二晶片的接触面的边缘暴露在第一 晶片，其中修整涉及第一晶片。 该方法包括：a）从具有对b）中计划的化学蚀刻的抗性的晶片中选择第二晶片，相对于第一晶片来说足以允许b）被执行; b）在将第一晶片接合到第二晶片之后，化学蚀刻第一晶片的边缘，以在第一晶片中形成完全搁置在第二晶片的接触面上并支撑第一晶片的剩余部分的基座; 以及c）使所述第一晶片变薄直到所述基座到达并受到攻击，以提供第一晶片的变薄部分。

    PROCESS OF TREATING DEFECTS DURING THE BONDING OF WAFERS
    4.
    发明申请
    PROCESS OF TREATING DEFECTS DURING THE BONDING OF WAFERS 有权
    在水泥粘结过程中处理缺陷的过程

    公开(公告)号：US20130323861A1

    公开(公告)日：2013-12-05

    申请号：US13957623

    申请日：2013-08-02

    Applicant: Soitec

    Inventor： Chrystelle Lagahe ,  Bernard Aspar

    IPC: H01L21/66

    CPC classification number: H01L22/12 ,  H01L21/2007

    Abstract: The invention concerns a process of preparing a thin layer to be transferred onto a substrate having a surface topology and, therefore, variations in altitude or level, in a direction perpendicular to a plane defined by the thin layer, this process comprising the formation on the thin layer of a layer of adhesive material, the thickness of which enables carrying out a plurality of polishing steps of its surface in order to eliminate any defect or void or almost any defect or void, in preparation for an assembly via a molecular kind of bonding with the substrate.

    Abstract translation: 本发明涉及一种在垂直于由薄层限定的平面的方向上制备要转移到具有表面拓扑结构并因此在高度或水平上的变化的基底上的薄层的方法，该方法包括在 薄层的粘合剂材料层，其厚度能够执行其表面的多个抛光步骤，以便消除任何缺陷或空隙或几乎任何缺陷或空隙，以准备通过分子种类的结合 与基材。

    STRUCTURE FOR RADIO FREQUENCY APPLICATIONS
    7.
    发明申请
    STRUCTURE FOR RADIO FREQUENCY APPLICATIONS 有权

    公开(公告)号：US20210280990A1

    公开(公告)日：2021-09-09

    申请号：US17330237

    申请日：2021-05-25

    Applicant: Soitec

    Inventor： Eric Desbonnets ,  Bernard Aspar

    IPC: H01Q23/00 ,  H01L21/762 ,  H01L29/66 ,  H01L29/786 ,  H01Q1/22

    Abstract: A structure for radiofrequency applications includes a high-resistivity support substrate having a front face defining a main plane, a charge-trapping layer disposed on the front face of the support substrate, a first dielectric layer disposed on the charge-trapping layer, an active layer disposed on the first dielectric layer, at least one buried electrode disposed above or in the charge-trapping layer. The buried electrode comprises a conductive layer and a second dielectric layer.

    Process of treating defects during the bonding of wafers
    9.
    发明授权
    Process of treating defects during the bonding of wafers 有权
    在晶片接合期间处理缺陷的过程

    公开(公告)号：US08722515B2

    公开(公告)日：2014-05-13

    申请号：US13957623

    申请日：2013-08-02

    Applicant: Soitec

    Inventor： Chrystelle Lagahe ,  Bernard Aspar

    IPC: H01L21/30 ,  H01L21/46

    CPC classification number: H01L22/12 ,  H01L21/2007

    Abstract: The invention concerns a process of preparing a thin layer to be transferred onto a substrate having a surface topology and, therefore, variations in altitude or level, in a direction perpendicular to a plane defined by the thin layer, this process comprising the formation on the thin layer of a layer of adhesive material, the thickness of which enables carrying out a plurality of polishing steps of its surface in order to eliminate any defect or void or almost any defect or void, in preparation for an assembly via a molecular kind of bonding with the substrate.

    Abstract translation: 本发明涉及一种在垂直于由薄层限定的平面的方向上制备要转移到具有表面拓扑结构并因此在高度或水平上的变化的基底上的薄层的方法，该方法包括在 薄层的粘合剂材料层，其厚度能够执行其表面的多个抛光步骤，以便消除任何缺陷或空隙或几乎任何缺陷或空隙，以准备通过分子种类的结合 与基材。

    HETEROSTRUCTURE AND METHOD OF FABRICATION
    10.
    发明申请
    HETEROSTRUCTURE AND METHOD OF FABRICATION 有权

    公开(公告)号：US20210058058A1

    公开(公告)日：2021-02-25

    申请号：US17075465

    申请日：2020-10-20

    Applicant: Soitec

    Inventor： Arnaud Castex ,  Daniel Delprat ,  Bernard Aspar ,  Ionut Radu

    IPC: H03H9/02 ,  H01L41/312 ,  H01L41/08 ,  H01L41/313 ,  H03H3/10

    Abstract: The present invention relates to a heterostructure, in particular, a piezoelectric structure, comprising a cover layer, in particular, a layer of piezoelectric material, the material of the cover layer having a first coefficient of thermal expansion, assembled to a support substrate, the support substrate having a second coefficient of thermal expansion substantially different from the first coefficient of thermal expansion, at an interface wherein the cover layer comprises at least a recess extending from the interface into the cover layer, and its method of fabrication.

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