公开(公告)号：US20240363522A1

公开(公告)日：2024-10-31

申请号：US18768225

申请日：2024-07-10

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Chao Chou ,  Kuo-Cheng Chiang ,  Shi Ning Ju ,  Wen-Ting Lan ,  Chih-Hao Wang

IPC分类号： H01L23/50 ,  H01L27/088 ,  H01L29/78

CPC分类号： H01L23/50 ,  H01L27/0886 ,  H01L29/785

摘要： Semiconductor devices and methods are provided. A method according to the present disclosure includes receiving a substrate that includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer; forming a plurality of fins over the third semiconductor layer; forming a trench between two of the plurality of fins; depositing a dummy material in the trench; forming a gate structure over channel regions of the plurality of the fins; forming source/drain features over source/drain regions of the plurality of the fins; bonding the substrate on a carrier wafer; removing the first and second semiconductor layers to expose the dummy material; removing the dummy material in the trench; depositing a conductive material in the trench; and bonding the substrate to a silicon substrate such that the conductive material is in contact with the silicon substrate. The trench extends through the third semiconductor layer and has a bottom surface on the second semiconductor layer.

公开(公告)号：US12087772B2

公开(公告)日：2024-09-10

申请号：US17476140

申请日：2021-09-15

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chung-Wei Hsu ,  Kuo-Cheng Chiang ,  Mao-Lin Huang ,  Lung-Kun Chu ,  Jia-Ni Yu ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC分类号： H01L21/02 ,  B82Y10/00 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/165 ,  H01L29/267 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L27/092 ,  H01L21/0259 ,  H01L21/28088 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823871 ,  H01L29/0665 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

摘要： A semiconductor device is provided. The semiconductor device includes first channel nanostructures in a first device region and second channel nanostructures in a second device region. The first channel nanostructures are disposed between first and second dielectric fins. The second channel nanostructures are disposed between first and third dielectric fins. A gate dielectric layer is formed to surround each of the first and the second channel nanostructures and over the first, the second and the third dielectric fins. A first work function layer is formed to surround each of the first channel nanostructures. A second work function layer is formed to surround each of the second channel nanostructures. A first gap is present between every adjacent first channel nanostructures and a second gap present is between every adjacent second channel nanostructures.

公开(公告)号：US12062721B2

公开(公告)日：2024-08-13

申请号：US17666240

申请日：2022-02-07

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shih-Cheng Chen ,  Kuo-Cheng Chiang ,  Zhi-Chang Lin

IPC分类号： H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

CPC分类号： H01L29/78612 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/0921 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

摘要： A semiconductor device according to the present disclosure includes an active region including a channel region and a source/drain region adjacent the channel region, a vertical stack of channel members over the channel region, a gate structure over and around the vertical stack of channel members, a bottom dielectric feature over the source/drain region, a source/drain feature over the bottom dielectric feature, and a germanium layer disposed between the bottom dielectric feature and the source/drain region.

公开(公告)号：US20240250141A1

公开(公告)日：2024-07-25

申请号：US18588727

申请日：2024-02-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Chao Chou ,  Kuo-Cheng Chiang ,  Shi Ning Ju ,  Wen-Ting Lan ,  Chih-Hao Wang

IPC分类号： H01L29/423 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

CPC分类号： H01L29/42392 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/66545

摘要： Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a conductive feature; a semiconductor stack formed over the dielectric layer, wherein the semiconductor stack including semiconductor layers stacked up and separated from each other; a first metal gate structure and a second metal gate structure formed over a channel region of the semiconductor stack, wherein the first metal gate structure and the second metal gate structure wrap each of the semiconductor layers of the semiconductor stack; and a first epitaxial feature disposed between the first metal gate structure and the second metal gate structure over a first source/drain region of the semiconductor stack, wherein the first epitaxial feature extends through the dielectric layer and contacts the conductive feature.

公开(公告)号：US12021136B2

公开(公告)日：2024-06-25

申请号：US18361556

申请日：2023-07-28

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kuan-Ting Pan ,  Huan-Chieh Su ,  Jia-Chuan You ,  Shi Ning Ju ,  Kuo-Cheng Chiang ,  Yi-Ruei Jhan ,  Li-Yang Chuang ,  Chih-Hao Wang

IPC分类号： H01L29/66 ,  H01L21/8234 ,  H01L29/06

CPC分类号： H01L29/6681 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/0669

摘要： A semiconductor structure includes a plurality of fin structures extending along a first direction, a plurality of gate structure segments positioned along a line extending in a second direction, the second direction being orthogonal to the first direction, wherein the gate structure segments are separated by dummy fin structures. The semiconductor structure further includes a conductive layer disposed over both the gate structure segments and the dummy fin structures to electrically connect at least some of the gate structure segments, and a cut feature aligned with one of the dummy fin structures and positioned to electrically isolate gate structure segments on both sides of the one of the dummy fin structures.

公开(公告)号：US12021123B2

公开(公告)日：2024-06-25

申请号：US17833145

申请日：2022-06-06

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kuo-Cheng Chiang ,  Shi Ning Ju ,  Kuan-Lun Cheng ,  Chih-Hao Wang ,  Cheng-Chi Chuang

IPC分类号： H01L29/417 ,  H01L23/522 ,  H01L23/528 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L29/41733 ,  H01L23/5226 ,  H01L23/5286 ,  H01L29/0653 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66553 ,  H01L29/6681 ,  H01L29/78696

摘要： A semiconductor structure includes a source/drain; one or more channel layers connected to the source/drain; a gate structure adjacent the source/drain and engaging each of the one or more channel layers; a first silicide layer over the source/drain; a source/drain contact over the first silicide layer; a power rail under the source/drain; one or more first dielectric layers between the source/drain and the power rail; and one or more second dielectric layers under the first silicide layer and on sidewalls of the source/drain, wherein the one or more second dielectric layers enclose an air gap.

公开(公告)号：US11916122B2

公开(公告)日：2024-02-27

申请号：US17370833

申请日：2021-07-08

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Zhi-Chang Lin ,  Kuan-Ting Pan ,  Shih-Cheng Chen ,  Jung-Hung Chang ,  Lo-Heng Chang ,  Chien-Ning Yao ,  Kuo-Cheng Chiang

IPC分类号： H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/66 ,  H01L29/40

CPC分类号： H01L29/42392 ,  H01L29/0665 ,  H01L29/401 ,  H01L29/6653 ,  H01L29/78696

摘要： A method for forming a gate all around transistor includes forming a plurality of semiconductor nanosheets. The method includes forming a cladding inner spacer between a source region of the transistor and a gate region of the transistor. The method includes forming sheet inner spacers between the semiconductor nanosheets in a separate deposition process from the cladding inner spacer.

公开(公告)号：US20230420520A1

公开(公告)日：2023-12-28

申请号：US18150524

申请日：2023-01-05

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tsung-Han Chuang ,  Zhi-Chang Lin ,  Shih-Cheng Chen ,  Jung-Hung Chang ,  Chien Ning Yao ,  Kai-Lin Chuang ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC分类号： H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L21/02 ,  H01L29/66

CPC分类号： H01L29/0847 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L21/02532 ,  H01L21/02639 ,  H01L29/775

摘要： In an embodiment, a device includes: first nanostructures; a first undoped semiconductor layer contacting a first dummy region of the first nanostructures; a first spacer on the first undoped semiconductor layer; a first source/drain region on the first spacer, the first source/drain region contacting a first channel region of the first nanostructures; and a first gate structure wrapped around the first channel region and the first dummy region of the first nanostructures.

公开(公告)号：US11854908B2

公开(公告)日：2023-12-26

申请号：US17662569

申请日：2022-05-09

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kuan-Ting Pan ,  Huan-Chieh Su ,  Zhi-Chang Lin ,  Shi Ning Ju ,  Yi-Ruei Jhan ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC分类号： H01L21/8238 ,  H01L21/02 ,  H01L21/311 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L21/823878 ,  H01L21/02603 ,  H01L21/31111 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78696

摘要： A method of fabricating a device includes forming a dummy gate over a plurality of fins. Thereafter, a first portion of the dummy gate is removed to form a first trench that exposes a first hybrid fin and a first part of a second hybrid fin. The method further includes filling the first trench with a dielectric material disposed over the first hybrid fin and over the first part of the second hybrid fin. Thereafter, a second portion of the dummy gate is removed to form a second trench and the second trench is filled with a metal layer. The method further includes etching-back the metal layer, where a first plane defined by a first top surface of the metal layer is disposed beneath a second plane defined by a second top surface of a second part of the second hybrid fin after the etching-back the metal layer.

公开(公告)号：US20230411219A1

公开(公告)日：2023-12-21

申请号：US18151598

申请日：2023-01-09

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Mao-Lin Huang ,  Lung-Kun Chu ,  Chung-Wei Hsu ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/775 ,  H01L29/66

CPC分类号： H01L21/823857 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/775 ,  H01L21/823807 ,  H01L29/66439 ,  H01L29/6684 ,  H01L29/4908

摘要： A semiconductor device includes a first channel region disposed in a first device region over a substrate; a first gate dielectric layer disposed over the first channel region; a second gate dielectric layer disposed over the second channel region; and a gate electrode disposed over the first gate dielectric layer. The first gate dielectric layer includes a first dipole dopant and the second gate dielectric layer includes a second dipole dopant embedded therein. A boundary between the first gate dielectric layer and the second gat dielectric layer contains the first dipole dopant and the second dipole dopant.