公开(公告)号：US20240363731A1

公开(公告)日：2024-10-31

申请号：US18768952

申请日：2024-07-10

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wei-Chih Kao ,  Hsin-Che Chiang ,  Yu-San Chien ,  Chun-Sheng Liang ,  Kuo-Hua Pan

IPC分类号： H01L29/66 ,  H01L21/033 ,  H01L21/324 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/78

CPC分类号： H01L29/66795 ,  H01L21/0337 ,  H01L21/324 ,  H01L21/762 ,  H01L21/76832 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/0922 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/785

摘要： An embodiment method includes: forming a semiconductor liner layer on exposed surfaces of a fin structure that extends above a dielectric isolation structure disposed over a substrate; forming a first capping layer to laterally surround a bottom portion of the semiconductor liner layer; forming a second capping layer over an upper portion of the semiconductor liner layer; and annealing the fin structure having the semiconductor liner layer, the first capping layer, and the second capping layer thereon, the annealing driving a dopant from the semiconductor liner layer into the fin structure, wherein a dopant concentration profile in a bottom portion of the fin structure is different from a dopant concentration profile in an upper portion of the fin structure.

公开(公告)号：US20240363397A1

公开(公告)日：2024-10-31

申请号：US18767134

申请日：2024-07-09

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ta-Chun Lin ,  Kuo-Hua Pan ,  Jhon Jhy Liaw

IPC分类号： H01L21/762 ,  G06F30/392 ,  H01L21/84 ,  H01L29/06

CPC分类号： H01L21/76283 ,  H01L21/845 ,  H01L29/0649 ,  G06F30/392

摘要： A semiconductor structure includes a first well doped with a first dopant and a second well doped with a second dopant different from the first dopant. From a top view, the first well includes a first base extending lengthwise along a direction, and a first letter-shaped portion and a second letter-shaped portion connected to the first base. From the top view, the second well includes a second base extending lengthwise along the direction and a third letter-shaped portion connected to the second base. The third letter-shaped portion extends into the first well and is keyed to the first letter-shaped portion and the second letter-shaped portion.

公开(公告)号：US11990525B2

公开(公告)日：2024-05-21

申请号：US17826816

申请日：2022-05-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ta-Chun Lin ,  Kuan-Lin Yeh ,  Chun-Jun Lin ,  Kuo-Hua Pan ,  Mu-Chi Chiang ,  Jhon Jhy Liaw

IPC分类号： H01L29/417 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78

CPC分类号： H01L29/41791 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/785 ,  H01L2029/7858

摘要： A first source/drain structure is disposed over a substrate. A second source/drain structure is disposed over the substrate. An isolation structure is disposed between the first source/drain structure and the second source/drain structure. The first source/drain structure and a first sidewall of the isolation structure form a first interface that is substantially linear. The second source/drain structure and a second sidewall of the isolation structure form a second interface that is substantially linear. A first source/drain contact surrounds the first source/drain structure in multiple directions. A second source/drain contact surrounds the second source/drain structure in multiple directions. The isolation structure is disposed between the first source/drain contact and the second source/drain contact.

公开(公告)号：US11749683B2

公开(公告)日：2023-09-05

申请号：US17728243

申请日：2022-04-25

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ta-Chun Lin ,  Kuan-Lin Yeh ,  Chun-Jun Lin ,  Kuo-Hua Pan ,  Mu-Chi Chiang

IPC分类号： H10B10/00 ,  H01L27/092 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/762 ,  H01L21/768

CPC分类号： H01L27/0924 ,  H01L21/762 ,  H01L21/76831 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823878 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7851 ,  H10B10/12

摘要： A semiconductor device includes a first active region and a second active region disposed over a substrate. A first source/drain component is grown on the first active region. A second source/drain component is grown on the second active region. An interlayer dielectric (ILD) is disposed around the first source/drain component and the second source/drain component. An isolation structure extends vertically through the ILD. The isolation structure separates the first source/drain component from the second source/drain component.

公开(公告)号：US20220293752A1

公开(公告)日：2022-09-15

申请号：US17826816

申请日：2022-05-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ta-Chun Lin ,  Kuan-Lin Yeh ,  Chun-Jun Lin ,  Kuo-Hua Pan ,  Mu-Chi Chiang ,  Jhon Jhy Liaw

IPC分类号： H01L29/417 ,  H01L29/08 ,  H01L29/78 ,  H01L29/06

摘要： A first source/drain structure is disposed over a substrate. A second source/drain structure is disposed over the substrate. An isolation structure is disposed between the first source/drain structure and the second source/drain structure. The first source/drain structure and a first sidewall of the isolation structure form a first interface that is substantially linear. The second source/drain structure and a second sidewall of the isolation structure form a second interface that is substantially linear. A first source/drain contact surrounds the first source/drain structure in multiple directions. A second source/drain contact surrounds the second source/drain structure in multiple directions. The isolation structure is disposed between the first source/drain contact and the second source/drain contact.

公开(公告)号：US20220238519A1

公开(公告)日：2022-07-28

申请号：US17717296

申请日：2022-04-11

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ta-Chun Lin ,  Kuo-Hua Pan ,  Jhon Jhy Liaw ,  Shien-Yang Wu

IPC分类号： H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/06

摘要： A method includes forming a first channel region, a second channel region, and a third channel region over a substrate, depositing a first interfacial layer over the first, second, and third channel regions, removing the first interfacial layer from the first and second channel regions, depositing a second interfacial layer over the first and second channel regions, thinning a thickness of the second interfacial layer over the first channel region, depositing a high-k dielectric layer over the first, second, and third channel regions, and forming a gate electrode layer over the first, second, and third channel regions.

公开(公告)号：US11239339B2

公开(公告)日：2022-02-01

申请号：US16397248

申请日：2019-04-29

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ta-Chun Lin ,  Jhon Jhy Liaw ,  Kuo-Hua Pan

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/165 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/762 ,  H01L21/308 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/786

摘要： A semiconductor structure includes a first active region over a substrate and extending along a first direction, a gate structure over the first active region and extending along a second direction substantially perpendicular to the first direction, a gate-cut feature abutting an end of the gate structure, and a channel isolation feature extending along the second direction and between the first active region and a second active region. The gate structure includes a metal electrode in direct contact with the gate-cut feature. The channel isolation feature includes a liner on sidewalls extending along the second direction and a dielectric fill layer between the sidewalls. The gate-cut feature abuts an end of the channel isolation feature and the dielectric fill layer is in direct contact with the gate-cut feature.

公开(公告)号：US20210384311A1

公开(公告)日：2021-12-09

申请号：US17409086

申请日：2021-08-23

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shien-Yang Wu ,  Ta-Chun Lin ,  Kuo-Hua Pan

IPC分类号： H01L29/423 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/3065 ,  H01L29/66 ,  H01L27/088 ,  H01L21/02 ,  H01L21/762 ,  H01L21/306 ,  H01L29/40 ,  H01L29/165

摘要： A method of manufacturing a device includes forming a plurality of stacks of alternating layers on a substrate, constructing a plurality of nanosheets from the plurality of stacks of alternating layers, and forming a plurality of gate dielectrics over the plurality of nanosheets, respectively. The method allows for the modulation of nanosheet width, thickness, spacing, and stack number and can be employed on single substrates. This design flexibility provides for design optimization over a wide tuning range of circuit performance and power usage.

公开(公告)号：US20210305084A1

公开(公告)日：2021-09-30

申请号：US17150725

申请日：2021-01-15

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ta-Chun Lin ,  Kuo-Hua Pan ,  Jhon Jhy Liaw

IPC分类号： H01L21/764 ,  H01L29/423 ,  H01L29/786 ,  H01L27/088 ,  H01L21/8234

摘要： A semiconductor structure includes a semiconductor fin protruding from a substrate, an S/D feature disposed over the semiconductor fin, and a first dielectric fin and a second dielectric fin disposed over the substrate, where the semiconductor fin is disposed between the first dielectric fin and the second dielectric fin, where a first air gap is enclosed by a first sidewall of the epitaxial S/D feature and the first dielectric fin, and where a second air gap is enclosed by a second sidewall of the epitaxial S/D feature and the second dielectric fin.

公开(公告)号：US20210202713A1

公开(公告)日：2021-07-01

申请号：US17181607

申请日：2021-02-22

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kuo-Hua Pan ,  Je-Wei Hsu ,  Hua Feng Chen ,  Jyun-Ming Lin ,  Chen-Huang Peng ,  Min-Yann Hsieh ,  Java Wu

IPC分类号： H01L29/66 ,  H01L29/08 ,  H01L21/311 ,  H01L29/78 ,  H01L29/45 ,  H01L21/768 ,  H01L29/417 ,  H01L23/485

摘要： A method includes forming a transistor, which includes forming a dummy gate stack over a semiconductor region, and forming an Inter-Layer Dielectric (ILD). The dummy gate stack is in the ILD, and the ILD covers a source/drain region in the semiconductor region. The method further includes removing the dummy gate stack to form a trench in the first ILD, forming a low-k gate spacer in the trench, forming a replacement gate dielectric extending into the trench, forming a metal layer to fill the trench, and performing a planarization to remove excess portions of the replacement gate dielectric and the metal layer to form a gate dielectric and a metal gate, respectively. A source region and a drain region are then formed on opposite sides of the metal gate.