公开(公告)号：US12299373B2

公开(公告)日：2025-05-13

申请号：US18447187

申请日：2023-08-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chi-Yu Lu ,  Hui-Zhong Zhuang ,  Pin-Dai Sue ,  Yi-Hsin Ko ,  Li-Chun Tien

IPC: G06F30/392 ,  G06F30/398

Abstract: A method of designing a semiconductor device including the operations of analyzing a vertical abutment between a first standard cell block and a second cell block and, if a mismatch is identified between the first standard cell block and the second cell block initiating the selection of a first modified cell block that reduces the mismatch and a spacing between the first modified cell block and the second cell block, the first modified cell block comprising a first abutment region having a continuous active region arranged along a first axis parallel to an edge of the vertical abutment, and replacing the first standard cell block with the first modified cell block to obtain a first modified layout design and devices manufactured according to the method.

公开(公告)号：US11526647B2

公开(公告)日：2022-12-13

申请号：US17115436

申请日：2020-12-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chi-Yu Lu ,  Ting-Wei Chiang ,  Hui-Zhong Zhuang ,  Jerry Chang Jui Kao ,  Pin-Dai Sue ,  Jiun-Jia Huang ,  Yu-Ti Su ,  Wei-Hsiang Ma

IPC: G06F30/394 ,  G03F1/70 ,  G03F1/36 ,  G06F30/398

Abstract: An integrated circuit includes a first type-one transistor, a second type-one transistor, a first type-two transistor, a second type-two transistor, a third type-one transistor, a fourth type-one transistor, and a fifth type-one transistor. The first type-one transistor has a gate configured to have a first supply voltage of a first power supply. The first type-two transistor has a gate configured to have a second supply voltage of the first power supply. The first active-region of the third type-one transistor is connected with an active-region of the first type-one transistor. The second active-region and the gate of the third type-one transistor are connected together. The first active-region of the fifth type-one transistor is connected with the gate of the third type-one transistor. The second active-region of the fifth type-one transistor is configured to have a first supply voltage of a second power supply.

公开(公告)号：US20220352166A1

公开(公告)日：2022-11-03

申请号：US17863175

申请日：2022-07-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shao-Lun Chien ,  Ting-Wei Chiang ,  Hui-Zhong Zhuang ,  Pin-Dai Sue

IPC: H01L27/092 ,  H01L23/528 ,  H01L23/522 ,  H01L21/765 ,  H01L21/8238

Abstract: An integrated circuit device includes a first power rail, a first active area extending in a first direction, and a plurality of gates contacting the first active area and extending in a second direction perpendicular to the first direction. A first transistor includes the first active area and a first one of the gates. The first transistor has a first threshold voltage (VT). A second transistor includes the first active area and a second one of the gates. The second transistor has a second VT different than the first VT. A tie-off transistor is positioned between the first transistor and the second transistor, and includes the first active area and a third one of the gates, wherein the third gate is connected to the first power rail.

公开(公告)号：US20210273093A1

公开(公告)日：2021-09-02

申请号：US16803261

申请日：2020-02-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ze-Sian Lu ,  Ting-Wei Chiang ,  Pin-Dai Sue ,  Jung-Hsuan Chen ,  Hui-Wen Li

IPC: H01L29/78 ,  H01L29/66

Abstract: A semiconductor device includes: a first multi-gate field effect transistor (FET) disposed over a substrate, the first multi-gate FET including a first active region; and a second multi-gate FET disposed over the first multi-gate FET, the second multi-gate FET including a second active region. The first active region and the second active region are not fully projected in a vertical direction perpendicular to the substrate.

公开(公告)号：US20180337167A1

公开(公告)日：2018-11-22

申请号：US16051241

申请日：2018-07-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chung-Te Lin ,  Ting-Wei Chiang ,  Hui-Zhong Zhuang ,  Pin-Dai Sue ,  Li-Chun Tien

IPC: H01L27/02 ,  H01L29/423 ,  G06F17/50 ,  H01L27/092 ,  H01L27/118

CPC classification number: H01L27/0207 ,  G06F17/5072 ,  H01L27/092 ,  H01L29/42376 ,  H01L2027/11875

Abstract: A layout includes a plurality of cells and at least one dummy gate electrode continuously extends across the cells. Since the dummy gate electrode is electrically conductive, the dummy gate electrode can be utilized for interconnecting the cells. That is, some signals may travel through the dummy gate electrode rather than through a metal one line or a metal two line. Therefore, an amount of metal one lines and/or metal two lines for interconnecting the cells can be reduced.

公开(公告)号：US11908851B2

公开(公告)日：2024-02-20

申请号：US17116915

申请日：2020-12-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Shun-Li Chen ,  Chung-Te Lin ,  Hui-Zhong Zhuang ,  Pin-Dai Sue ,  Jung-Chan Yang

IPC: H01L29/66 ,  H01L27/02 ,  H01L27/092 ,  H01L23/522 ,  H01L23/528 ,  H01L21/285 ,  H01L23/532 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/417

CPC classification number: H01L27/0207 ,  H01L21/28525 ,  H01L21/28568 ,  H01L21/823821 ,  H01L21/823871 ,  H01L23/5221 ,  H01L23/5286 ,  H01L23/53209 ,  H01L23/53271 ,  H01L27/0924 ,  H01L29/41791 ,  H01L29/4238 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/66795

Abstract: A method for forming a semiconductor device includes: forming a fin structure protruding from a substrate of the semiconductor device; forming a first conductive rail on the substrate, wherein a side of the first conductive rail facing the fin structure has a first recess and a second recess; forming a first conductive line in a same layer as the first conductive rail by filling a first conductive material into the first recess, wherein the first conductive line extends across the fin structure and wraps a portion of the fin structure; and forming a second conductive line in the same layer as the first conductive rail by filling a second conductive material into the second recess, wherein the second conductive line extends across the fin structure and contacts another portion of the fin structure.

公开(公告)号：US11855619B2

公开(公告)日：2023-12-26

申请号：US16744110

申请日：2020-01-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Tzung-Yo Hung ,  Pin-Dai Sue ,  Chien-Chi Tien ,  Ting-Wei Chiang

IPC: H03K17/00 ,  H03K17/687 ,  H03K19/0948 ,  G05F3/16 ,  H03K19/0185 ,  H01L21/02 ,  H01L21/283 ,  H01L21/822 ,  H01L29/423 ,  H01L29/06 ,  B82Y10/00

CPC classification number: H03K17/6872 ,  G05F3/16 ,  H01L21/02104 ,  H01L21/283 ,  H01L21/822 ,  H01L29/0669 ,  H01L29/42312 ,  H03K19/018571 ,  H03K19/0948 ,  B82Y10/00

Abstract: An integrated circuit device includes: an integrated circuit module; a first field-effect transistor coupled between the integrated circuit module and a first reference voltage, and controlled by a first controlled signal; and a second field-effect transistor coupled between the integrated circuit module and the first reference voltage; wherein the second field-effect transistor is a complementary field-effect transistor of the first field-effect transistor, and the first field-effect transistor and the second field-effect transistor are configured to generate a second reference voltage for the integrated circuit module according to the first control signal.

公开(公告)号：US11574107B2

公开(公告)日：2023-02-07

申请号：US17339162

申请日：2021-06-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Pin-Dai Sue ,  Po-Hsiang Huang ,  Fong-Yuan Chang ,  Chi-Yu Lu ,  Sheng-Hsiung Chen ,  Chin-Chou Liu ,  Lee-Chung Lu ,  Yen-Hung Lin ,  Li-Chun Tien ,  Yi-Kan Cheng

IPC: G06F30/00 ,  G06F30/392 ,  G06F30/394 ,  G06F111/20

Abstract: A method of manufacturing a semiconductor device includes forming a transistor layer with an M*1st layer that overlays the transistor layer with one or more first conductors that extend in a first direction. Forming an M*2nd layer that overlays the M*1st layer with one or more second conductors which extend in a second direction. Forming a first pin in the M*2nd layer representing an output pin of a cell region. Forming a long axis of the first pin substantially along a selected one of the one or more second conductors. Forming a majority of the total number of pins in the M*1st layer, the forming including: forming second, third, fourth and fifth pins in the M*1st layer representing corresponding input pins of the circuit; and forming long axes of the second to fifth pins substantially along corresponding ones of the one or more first conductors.

公开(公告)号：US10727177B2

公开(公告)日：2020-07-28

申请号：US16174953

申请日：2018-10-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chung-Te Lin ,  Ting-Wei Chiang ,  Hui-Zhong Zhuang ,  Li-Chun Tien ,  Pin-Dai Sue

IPC: H01L23/522 ,  H01L27/02 ,  H01L27/118

Abstract: A device includes gates and a first conductive segment. A first distance is present between a first gate of the gates and the first conductive segment. A second distance is present between a second gate of the gates and the first conductive segment. The first distance is greater than the second distance.

公开(公告)号：US20140203378A1

公开(公告)日：2014-07-24

申请号：US14220930

申请日：2014-03-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Tsong-Hua Ou ,  Shu-Min Chen ,  Pin-Dai Sue ,  Li-Chun Tien ,  Ru-Gun Liu

IPC: H01L27/088

CPC classification number: H01L27/0886 ,  G06F17/5068 ,  H01L21/823431 ,  H01L27/0924 ,  H01L27/11803

Abstract: A method of designing a standard cell includes determining a minimum fin pitch of semiconductor fins in the standard cell, wherein the semiconductor fins are portions of FinFETs; and determining a minimum metal pitch of metal lines in a bottom metal layer over the standard cell, wherein the minimum metal pitch is greater than the minimum fin pitch. The standard cell is placed in an integrated circuit and implemented on a semiconductor wafer.

Abstract translation: 设计标准单元的方法包括确定标准单元中的半导体鳍片的最小鳍间距，其中半导体鳍片是FinFET的部分; 以及确定所述标准单元上的底部金属层中的金属线的最小金属间距，其中所述最小金属间距大于所述最小鳍间距。 将标准单元放置在集成电路中并在半导体晶片上实现。