公开(公告)号：US11916070B2

公开(公告)日：2024-02-27

申请号：US17345452

申请日：2021-06-11

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Te-Hsin Chiu ,  Kam-Tou Sio ,  Shang-Wei Fang ,  Wei-Cheng Lin ,  Jiann-Tyng Tzeng

IPC分类号： H01L27/088 ,  H01L29/06 ,  G06F30/392 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/033 ,  H01L29/66

CPC分类号： H01L27/0886 ,  G06F30/392 ,  H01L21/0334 ,  H01L21/823431 ,  H01L29/0665 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

摘要： Disclosed are semiconductor devices including a substrate, a first transistor formed over a first portion of the substrate, wherein the first transistor comprises a first nanosheet stack including N nanosheets and a second transistor over a second portion of the substrate, wherein the second transistor comprises a second nanosheet stack including M nanosheets, wherein N is different from M in which the first and second nanosheet stacks are formed on first and second substrate regions that are vertically offset from one another.

公开(公告)号：US20230255012A1

公开(公告)日：2023-08-10

申请号：US18300513

申请日：2023-04-14

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Te-Hsin Chiu ,  Meng-Han Lin ,  Wei Cheng Wu

IPC分类号： H10B10/00 ,  H01L23/528 ,  G11C29/50 ,  G11C29/08 ,  G11C29/04 ,  G11C29/12 ,  G06F30/39 ,  G06F30/398

CPC分类号： H10B10/12 ,  H01L23/528 ,  G11C29/50 ,  G11C29/08 ,  G11C29/04 ,  G11C29/12005 ,  G06F30/39 ,  G06F30/398 ,  G11C2029/5006 ,  G11C2029/0403 ,  G11C2029/1206

摘要： Some examples relate to a method. In this method, a metal isolation test circuit, which is disposed on a semiconductor substrate, is received. The metal isolation test circuit includes a plurality of transistors and an interconnect structure coupled to the plurality of transistors. The interconnect structure includes a plurality of pins. A first voltage bias is applied across first and second pins of the plurality of pins, and a first leakage current is measured while the first voltage bias is applied. A process or a design rule by which the metal isolation test circuit is made is characterized based on the first leakage current.

公开(公告)号：US11675952B2

公开(公告)日：2023-06-13

申请号：US17345361

申请日：2021-06-11

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shih-Wei Peng ,  Te-Hsin Chiu ,  Jiann-Tyng Tzeng

IPC分类号： G06F30/392 ,  H01L23/50 ,  H01L27/02 ,  H01L21/768 ,  H01L23/528 ,  G06F30/398

CPC分类号： G06F30/392 ,  G06F30/398 ,  H01L21/768 ,  H01L23/50 ,  H01L23/5286 ,  H01L27/0207

摘要： An integrated circuit includes a first power rail, a first signal line, a first transistor and a second transistor. The first power rail is on a back-side of a substrate and is configured to supply a first supply voltage. The first signal line is on the back-side of the substrate and is separated from the first power rail. The first transistor has a first active region in a front-side of the substrate. The first active region is overlapped by the first power rail and is electrically coupled to the first power rail. The second transistor has a second active region that is in the front-side of the substrate. The second active region is separated from the first active region, is overlapped by the first signal line, and is configured to receive the first supply voltage of the first power rail through the first active region of the first transistor.

公开(公告)号：US11532621B2

公开(公告)日：2022-12-20

申请号：US17351392

申请日：2021-06-18

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei Cheng Wu

IPC分类号： H01L29/00 ,  H01L27/092 ,  H01L29/49 ,  H01L29/423 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/28 ,  H01L21/762 ,  H01L29/40 ,  H01L29/51

摘要： The present disclosure relates to an integrated chip. The integrated chip includes a source region and a drain region disposed within an upper surface of a substrate. One or more dielectric materials are disposed within a trench defined by sidewalls of the substrate that surround the source region and the drain region. The one or more dielectric materials include one or more interior surfaces defining a recess within the one or more dielectric materials. A gate structure is disposed over the substrate between the source region and the drain region. The gate structure includes a first gate material over the upper surface of the substrate and a second gate material. The second gate material completely fills the recess as viewed along a cross-sectional view.

公开(公告)号：US20220367498A1

公开(公告)日：2022-11-17

申请号：US17874416

申请日：2022-07-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei Cheng Wu

IPC分类号： H01L27/11536 ,  H01L29/788 ,  H01L29/423 ,  H01L29/49 ,  H01L29/08 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/28 ,  H01L21/311 ,  H01L21/768 ,  H01L21/762 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/027 ,  H01L27/11521

摘要： Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC comprises a memory region and a logic region integrated in a substrate. A plurality of memory cell structures is disposed on the memory region. Each memory cell structure of the plurality of memory cell structures comprises a control gate electrode disposed over the substrate, a select gate electrode disposed on one side of the control gate electrode, and a spacer between the control gate electrode and the select gate electrode. A contact etch stop layer (CESL) is disposed along an upper surface of the substrate, extending upwardly along and in direct contact with a sidewall surface of the select gate electrode within the memory region. A lower inter-layer dielectric layer is disposed on the CESL between the plurality of memory cell structures within the memory region.

公开(公告)号：US20220122993A1

公开(公告)日：2022-04-21

申请号：US17075704

申请日：2020-10-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Te-Hsin Chiu ,  Jiann-Tyng Tzeng ,  Shih-Wei Peng ,  Wei-An Lai

IPC分类号： H01L27/11 ,  G11C11/412 ,  G11C5/02 ,  H01L27/092

摘要： A memory device is provided. The memory device includes first and second pull-up transistors. The first pull-up transistor is disposed over a semiconductor substrate, and including a first gate structure and two first source/drain structures at opposite sides of the first gate structure. The second pull-up transistor is laterally spaced apart from the first pull-up transistor, and including a second gate structure and two second source/drain structures at opposite sides of the second gate structure. The first and second gate structures extend along a first direction and laterally spaced apart from each other along a second direction intersected with the first direction. The first gate structure further extends along a sidewall of one of the second source/drain structures, and the second gate structure further extends along a sidewall of one of the first source/drain structures.

公开(公告)号：US11302631B2

公开(公告)日：2022-04-12

申请号：US16943896

申请日：2020-07-30

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Te-Hsin Chiu ,  Shih-Wei Peng ,  Jiann-Tyng Tzeng

IPC分类号： H01L23/522 ,  H01L27/02 ,  H01L27/118 ,  H01L21/768

摘要： An integrated circuit cell is provided, which may include a substrate with a front side and a back side, an active region, a first via, and first, second and third conductive layers. A portion of the active region may be formed within the substrate. The first via and the first, second and third conductive layers are on the back side. The second and third conductive layers may be located further away from the substrate in a first direction than the first and second conductive layers, respectively. The depth of the first via may be greater than a distance between the second conductive layer and the third conductive layer. The integrated circuit cell may include a cell height in a second direction substantially perpendicular to the first direction. A width of the first via along the second direction may be between about 0.05 to about 0.25 times the cell height.

公开(公告)号：US12131998B2

公开(公告)日：2024-10-29

申请号：US18298172

申请日：2023-04-10

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Te-Hsin Chiu ,  Kam-Tou Sio ,  Shih-Wei Peng ,  Wei-Cheng Lin ,  Jiann-Tyng Tzeng

IPC分类号： H01L23/528 ,  H01L21/8238 ,  H01L27/092

CPC分类号： H01L23/5286 ,  H01L21/823871 ,  H01L27/092

摘要： A method of fabricating an integrated circuit includes fabricating a set of transistors in a front-side of a substrate, fabricating a first set of vias in a back-side of the substrate, depositing a first set of conductive structures on the back-side on a first level, depositing a second set of conductive structures on the back-side on a second level thereby forming a set of power rails, fabricating a second set of vias in the back-side, and depositing a third set of conductive structures on the back-side on a third level. The first set of vias is electrically coupled to the set of transistors. The second set of vias is electrically coupled to the first and third set of conductive structures. A first structure of the first set of conductive structures is electrically coupled to a first via of the first set of vias.

公开(公告)号：US20240321890A1

公开(公告)日：2024-09-26

申请号：US18673632

申请日：2024-05-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Te-Hsin Chiu ,  Kam-Tou Sio ,  Jiann-Tyng Tzeng

IPC分类号： H01L27/092 ,  H01L21/764 ,  H01L21/8238 ,  H01L23/528 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L27/0924 ,  H01L21/764 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L23/5286 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/78618 ,  H01L29/78696

摘要： A semiconductor device includes a semiconductor substrate. The semiconductor device includes a first fin protruding from the semiconductor substrate and extending along a first direction. The semiconductor device includes a second fin protruding from the semiconductor substrate and extending along the first direction. A first epitaxial source/drain region coupled to the first fin and a second epitaxial source/drain region coupled to the second fin are laterally spaced apart from each other by an air void.

公开(公告)号：US12021021B2

公开(公告)日：2024-06-25

申请号：US17459697

申请日：2021-08-27

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Te-Hsin Chiu ,  Shih-Wei Peng ,  Wei-Cheng Lin ,  Jiann-Tyng Tzeng

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02

CPC分类号： H01L23/5226 ,  H01L21/76895 ,  H01L23/528 ,  H01L27/0207

摘要： An integrated circuit structure is disclosed, including a gate, a first conductive line and a pair of second conductive lines, and a first feed-through via. The gate is disposed on a front side of the integrated circuit structure and extends in a first direction on a first side of a dielectric layer. The first conductive line and a pair of second conductive lines are disposed on a second side, opposite of the first side, of the dielectric layer and on a back side, opposite of the front side, of the integrated circuit structure. The first conductive line is interposed between the pair of second conductive lines in a layout view. The first feed-through via extends through the dielectric layer in a second direction different from the first direction. The first feed-through via couples the gate to the first conductive line.