公开(公告)号：US11450638B2

公开(公告)日：2022-09-20

申请号：US17009648

申请日：2020-09-01

Applicant: Texas Instruments Incorporated

Inventor： Dibyajat Mishra ,  Ashok Prabhu ,  Tomoko Noguchi ,  Luu Thanh Nguyen ,  Anindya Poddar ,  Makoto Yoshino ,  Hau Nguyen

IPC: H01L23/00 ,  H01L23/495 ,  H01L23/31

Abstract: A microelectronic device has a pillar connected to an external terminal by an intermetallic joint. Either the pillar or the external terminal, or both, include copper in direct contact with the intermetallic joint. The intermetallic joint includes at least 90 weight percent of at least one copper-tin intermetallic compound. The intermetallic joint is free of voids having a combined volume greater than 10 percent of a volume of the intermetallic joint; and free of a void having a volume greater than 5 percent of the volume of the intermetallic joint. The microelectronic device may be formed using solder which includes at least 93 weight percent tin, 0.5 weight percent to 5.0 weight percent silver, and 0.4 weight percent to 1.0 weight percent copper, to form a solder joint between the pillar and the external terminal, followed by thermal aging to convert the solder joint to the intermetallic joint.

公开(公告)号：US10763231B2

公开(公告)日：2020-09-01

申请号：US16047888

申请日：2018-07-27

Applicant: Texas Instruments Incorporated

Inventor： Dibyajat Mishra ,  Ashok Prabhu ,  Tomoko Noguchi ,  Luu Thanh Nguyen ,  Anindya Poddar ,  Makoto Yoshino ,  Hau Nguyen

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/495

Abstract: A microelectronic device has a pillar connected to an external terminal by an intermetallic joint. Either the pillar or the external terminal, or both, include copper in direct contact with the intermetallic joint. The intermetallic joint includes at least 90 weight percent of at least one copper-tin intermetallic compound. The intermetallic joint is free of voids having a combined volume greater than 10 percent of a volume of the intermetallic joint; and free of a void having a volume greater than 5 percent of the volume of the intermetallic joint. The microelectronic device may be formed using solder which includes at least 93 weight percent tin, 0.5 weight percent to 5.0 weight percent silver, and 0.4 weight percent to 1.0 weight percent copper, to form a solder joint between the pillar and the external terminal, followed by thermal aging to convert the solder joint to the intermetallic joint.

公开(公告)号：US20180127266A1

公开(公告)日：2018-05-10

申请号：US15867563

申请日：2018-01-10

Applicant: Texas Instruments Incorporated

Inventor： Kurt Peter Wachtler ,  Makoto Yoshino ,  Ayumu Kuroda ,  Brian E. Goodlin ,  Karen Kirmse ,  Benjamin Cook ,  Genki Yano ,  Stuart Jacobsen

IPC: B81B7/00

CPC classification number: B81B7/0048 ,  B81B7/0054 ,  B81B2207/012 ,  B81B2207/097 ,  B81B2207/99 ,  B81C1/00325 ,  B81C2203/0136 ,  B81C2203/0154 ,  H01L23/3107 ,  H01L23/3135 ,  H01L23/49541 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A packaged micro-electro-mechanical system (MEMS) device (100) comprises a circuitry chip (101) attached to the pad (110) of a substrate with leads (111), and a MEMS (150) vertically attached to the chip surface by a layer (140) of low modulus silicone compound. On the chip surface, the MEMS device is surrounded by a polyimide ring (130) with a surface phobic to silicone compounds. A dome-shaped glob (160) of cured low modulus silicone material covers the MEMS and the MEMS terminal bonding wire spans (180); the glob is restricted to the chip surface area inside the polyimide ring and has a surface non-adhesive to epoxy-based molding compounds. A package (190) of polymeric molding compound encapsulates the vertical assembly of the glob embedding the MEMS, the circuitry chip, and portions of the substrate; the molding compound is non-adhering to the glob surface yet adhering to all other surfaces.

公开(公告)号：US20170236754A1

公开(公告)日：2017-08-17

申请号：US15585519

申请日：2017-05-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Makoto Shibuya ,  Makoto Yoshino

IPC: H01L21/78 ,  H01L21/56 ,  H01L23/498 ,  H01L23/00 ,  H01L23/495

CPC classification number: H01L21/78 ,  H01L21/561 ,  H01L21/565 ,  H01L23/492 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49551 ,  H01L23/49575 ,  H01L23/49861 ,  H01L24/37 ,  H01L24/40 ,  H01L2224/37147 ,  H01L2224/40245 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/8485

Abstract: A circuit includes a conductive clip coupled to at least one component in the circuit. At least one lead portion is located on an end of the clip. The circuit further includes a first lead frame having at least one opening sized to receive the at least one lead portion. The at least one lead portion is received in the at least one opening and the at least one lead portion is an external conductor of the circuit.

公开(公告)号：US20160336256A1

公开(公告)日：2016-11-17

申请号：US14709074

申请日：2015-05-11

Applicant: Texas Instruments Incorporated

Inventor： Makoto Shibuya ,  Makoto Yoshino

IPC: H01L23/495 ,  H01L21/56 ,  H01L21/78 ,  H01L23/538 ,  H01L21/48

CPC classification number: H01L21/78 ,  H01L21/561 ,  H01L21/565 ,  H01L23/492 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49551 ,  H01L23/49575 ,  H01L23/49861 ,  H01L24/37 ,  H01L24/40 ,  H01L2224/37147 ,  H01L2224/40245 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/8485

Abstract: A circuit includes a conductive clip coupled to at least one component in the circuit. At least one lead portion is located on an end of the clip. The circuit further includes a first lead frame having at least one opening sized to receive the at least one lead portion. The at least one lead portion is received in the at least one opening and the at least one lead portion is an external conductor of the circuit.

Abstract translation: 电路包括耦合到电路中的至少一个部件的导电夹。 至少一个引线部分位于夹子的一端。 电路还包括具有至少一个开口的第一引线框架，其尺寸被设计成可容纳至少一个引线部分。 所述至少一个引线部分被容纳在所述至少一个开口中，并且所述至少一个引线部分是所述电路的外部导体。

公开(公告)号：US12021019B2

公开(公告)日：2024-06-25

申请号：US17515176

申请日：2021-10-29

Applicant: Texas Instruments Incorporated

Inventor： Anindya Poddar ,  Ashok Surendra Prabhu ,  Edgar Dorotyao Balidoy ,  Hau Nguyen ,  Makoto Yoshino ,  Ming Li

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H05K1/02

CPC classification number: H01L23/49861 ,  H01L21/4839 ,  H01L21/565 ,  H01L23/49844 ,  H01L24/48 ,  H05K1/0204 ,  H01L2224/48177 ,  H01L2224/48178 ,  H01L2224/48248 ,  H01L2224/48465 ,  H01L2924/1811 ,  H01L2924/182

Abstract: A described example includes: a package substrate having a die pad with a die side surface and having an opposite backside surface, having leads arranged along two opposite sides and having die pad straps extending from two opposing ends of the die pad. The leads lie in a first plane, a portion of the die pad straps lie in a second plane that is spaced from the first plane and located closer to the die pad, and the die pad lies in a third plane that is spaced from and parallel to the second plane in a direction away from the first plane. A semiconductor die is mounted to the die side surface and mold compound covers the semiconductor die, a portion of the leads, and the die side surface of the die pad, and the backside surface of the die pad exposed from the mold compound.

公开(公告)号：US20240347441A1

公开(公告)日：2024-10-17

申请号：US18753858

申请日：2024-06-25

Applicant: Texas Instruments Incorporated

Inventor： Anindya Poddar ,  Ashok Surendra Prabhu ,  Edgar Dorotyao Balidoy ,  Hau Nguyen ,  Makoto Yoshino ,  MING LI

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H05K1/02

CPC classification number: H01L23/49861 ,  H01L21/4839 ,  H01L21/565 ,  H01L23/49844 ,  H01L24/48 ,  H05K1/0204 ,  H01L2224/48177 ,  H01L2224/48178 ,  H01L2224/48248 ,  H01L2224/48465 ,  H01L2924/1811 ,  H01L2924/182

Abstract: A described example includes: a package substrate having a die pad with a die side surface and having an opposite backside surface, having leads arranged along two opposite sides and having die pad straps extending from two opposing ends of the die pad. The leads lie in a first plane, a portion of the die pad straps lie in a second plane that is spaced from the first plane and located closer to the die pad, and the die pad lies in a third plane that is spaced from and parallel to the second plane in a direction away from the first plane. A semiconductor die is mounted to the die side surface and mold compound covers the semiconductor die, a portion of the leads, and the die side surface of the die pad, and the backside surface of the die pad exposed from the mold compound.

公开(公告)号：US12046542B2

公开(公告)日：2024-07-23

申请号：US17246056

申请日：2021-04-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Makoto Shibuya ,  Makoto Yoshino ,  Kengo Aoya

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/49

CPC classification number: H01L23/49568 ,  H01L21/4825 ,  H01L21/4885 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/49 ,  H01L23/49506 ,  H01L23/4952 ,  H01L23/49582

Abstract: In some examples, a semiconductor package includes a semiconductor die having a device side and a non-device side opposing the device side. The device side has a circuit formed therein. The package includes a first conductive member having a first surface coupled to the non-device side of the semiconductor die and a second surface opposing the first surface. The second surface is exposed to a top surface of the semiconductor package. The package includes a second conductive member exposed to an exterior of the semiconductor package and coupled to the device side of the semiconductor die. The package includes a plurality of wirebonded members coupled to the second surface of the first conductive member and exposed to the exterior of the semiconductor package. At least one of the wirebonded members in the plurality of wirebonded members has a gauge of at least 5 mils.

公开(公告)号：US20240055327A1

公开(公告)日：2024-02-15

申请号：US17818395

申请日：2022-08-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Makoto Yoshino ,  Hiroki Kawano ,  Hau Nguyen

IPC: H01L23/495 ,  H01L21/48

CPC classification number: H01L23/4951 ,  H01L23/49555 ,  H01L21/4842

Abstract: A method for making a semiconductor device is provided. The method generally includes forming a package having a first plurality of leads extending from a first side of the package, the package disposed on a leadframe. The method generally includes making a first cut adjacent to a first side of a first lead of the first plurality of leads, the first side extending from the first side of the package. The method generally includes making a second cut adjacent to a second side of the first lead of the first plurality of the lead, the second side of the lead opposite the first side of the lead and extending from the first side of the package.

公开(公告)号：US11498831B2

公开(公告)日：2022-11-15

申请号：US16941138

申请日：2020-07-28

Applicant: Texas Instruments Incorporated

Inventor： Kurt Peter Wachtler ,  Makoto Yoshino ,  Ayumu Kuroda ,  Brian E. Goodlin ,  Karen Kirmse ,  Benjamin Cook ,  Genki Yano ,  Stuart Jacobsen

IPC: B81B7/00 ,  B81C1/00 ,  H01L23/31 ,  H01L23/495

Abstract: A packaged micro-electro-mechanical system (MEMS) device (100) comprises a circuitry chip (101) attached to the pad (110) of a substrate with leads (111), and a MEMS (150) vertically attached to the chip surface by a layer (140) of low modulus silicone compound. On the chip surface, the MEMS device is surrounded by a polyimide ring (130) with a surface phobic to silicone compounds. A dome-shaped glob (160) of cured low modulus silicone material covers the MEMS and the MEMS terminal bonding wire spans (180); the glob is restricted to the chip surface area inside the polyimide ring and has a surface non-adhesive to epoxy-based molding compounds. A package (190) of polymeric molding compound encapsulates the vertical assembly of the glob embedding the MEMS, the circuitry chip, and portions of the substrate; the molding compound is non-adhering to the glob surface yet adhering to all other surfaces.