公开(公告)号：US20190252016A1

公开(公告)日：2019-08-15

申请号：US15967511

申请日：2018-04-30

Applicant: Texas Instruments Incorporated

Inventor： John Anthony Rodriguez ,  Richard Allen Bailey

IPC: G11C11/22 ,  H04L9/32

CPC classification number: G11C11/2275 ,  G11C11/221 ,  G11C11/2273 ,  H04L9/3278

Abstract: A method of generating a random number from an electronic circuit memory and/or a system with the electronic circuit memory. The memory comprises a block of ferroelectric two transistor, two capacitor (2T-2C), memory cells. The method comprises: (i) first, writing a predetermined programming pattern to the block cells in a one transistor, one-capacitor (1T-1C) mode, thusly writing, per cell, a same data state to both a first and second sub-cell of the cell; (ii) second, reading the cells in a 2T-2C mode to generate a random number comprising a random bit from each of the cells; (iii) third, restoring the random number into the cells in a 2T-2C mode, thusly writing, per cell, a complementary data state to both a first and second sub-cell of the cell, responsive to a respective random number bit; and fourth, imprinting the random number in each cell in the block.

公开(公告)号：US11495607B2

公开(公告)日：2022-11-08

申请号：US16056827

申请日：2018-08-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Huang-Chun Wen ,  Richard Allen Bailey ,  Antonio Guillermo Acosta ,  John A. Rodriguez ,  Scott Robert Summerfelt ,  Kemal Tamer San

IPC: H01L27/11507 ,  H01L21/02 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00

Abstract: Curing of a passivation layer applied to the surface of a ferroelectric integrated circuit so as to enhance the polarization characteristics of the ferroelectric structures. A passivation layer, such as a polyimide, is applied to the surface of the ferroelectric integrated circuit after fabrication of the active devices. The passivation layer is cured by exposure to a high temperature, below the Curie temperature of the ferroelectric material, for a short duration such as on the order of ten minutes. Variable frequency microwave energy may be used to effect such curing. The cured passivation layer attains a tensile stress state, and as a result imparts a compressive stress upon the underlying ferroelectric material. Polarization may be further enhanced by polarizing the ferroelectric material prior to the cure process.

公开(公告)号：US10424361B2

公开(公告)日：2019-09-24

申请号：US15967511

申请日：2018-04-30

Applicant: Texas Instruments Incorporated

Inventor： John Anthony Rodriguez ,  Richard Allen Bailey

IPC: G11C11/22 ,  H04L9/32

Abstract: A method of generating a random number from an electronic circuit memory and/or a system with the electronic circuit memory. The memory comprises a block of ferroelectric two transistor, two capacitor (2T-2C), memory cells. The method comprises: (i) first, writing a predetermined programming pattern to the block cells in a one transistor, one-capacitor (1T-1C) mode, thusly writing, per cell, a same data state to both a first and second sub-cell of the cell; (ii) second, reading the cells in a 2T-2C mode to generate a random number comprising a random bit from each of the cells; (iii) third, restoring the random number into the cells in a 2T-2C mode, thusly writing, per cell, a complementary data state to both a first and second sub-cell of the cell, responsive to a respective random number bit; and fourth, imprinting the random number in each cell in the block.

公开(公告)号：US09824769B2

公开(公告)日：2017-11-21

申请号：US15146049

申请日：2016-05-04

Applicant: Texas Instruments Incorporated

Inventor： Sunil Kumar Dusa ,  Richard Allen Bailey ,  Archana Venugopal ,  John Anthony Rodriguez ,  Michael Allen Ball

IPC: G11C17/18 ,  G11C17/16

CPC classification number: G11C17/18 ,  G11C17/165

Abstract: A fuse-programmable register or memory location having a plurality of fusible links of differing electrical characteristics in parallel. In one embodiment, three fusible links with different resistances are provided, such that application of a programming voltage non-uniformly distributes the current among the links, allowing varying voltages to selectively blow one or more of the links. Sensing of the programmed state is performed by applying a voltage across the parallel links and measuring the current in comparison with a plurality of reference currents. Reduction in the overhead chip area per bit and in the serial data communication latency are obtained.

公开(公告)号：US20180374861A1

公开(公告)日：2018-12-27

申请号：US16056827

申请日：2018-08-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Huang-Chun Wen ,  Richard Allen Bailey ,  Antonio Guillemo Acosta ,  John A. Rodriguez ,  Scott Robert Summerfelt ,  Kemal Tamer San

IPC: H01L27/11507 ,  H01L21/02 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

Abstract: Curing of a passivation layer applied to the surface of a ferroelectric integrated circuit so as to enhance the polarization characteristics of the ferroelectric structures. A passivation layer, such as a polyimide, is applied to the surface of the ferroelectric integrated circuit after fabrication of the active devices. The passivation layer is cured by exposure to a high temperature, below the Curie temperature of the ferroelectric material, for a short duration such as on the order of ten minutes. Variable frequency microwave energy may be used to effect such curing. The cured passivation layer attains a tensile stress state, and as a result imparts a compressive stress upon the underlying ferroelectric material. Polarization may be further enhanced by polarizing the ferroelectric material prior to the cure process.

公开(公告)号：US10153053B2

公开(公告)日：2018-12-11

申请号：US15787905

申请日：2017-10-19

Applicant: Texas Instruments Incorporated

Inventor： Sunil Kumar Dusa ,  Richard Allen Bailey ,  Archana Venugopal ,  John Anthony Rodriguez ,  Michael Allen Ball

IPC: G11C17/18 ,  G11C17/16

Abstract: A fuse-programmable register or memory location having a plurality of fusible links of differing electrical characteristics in parallel. In one embodiment, three fusible links with different resistances are provided, such that application of a programming voltage non-uniformly distributes the current among the links, allowing varying voltages to selectively blow one or more of the links. Sensing of the programmed state is performed by applying a voltage across the parallel links and measuring the current in comparison with a plurality of reference currents. Reduction in the overhead chip area per bit and in the serial data communication latency are obtained.

公开(公告)号：US20180040381A1

公开(公告)日：2018-02-08

申请号：US15787905

申请日：2017-10-19

Applicant: Texas Instruments Incorporated

Inventor： Sunil Kumar Dusa ,  Richard Allen Bailey ,  Archana Venugopal ,  John Anthony Rodriguez ,  Michael Allen Ball

IPC: G11C17/18 ,  G11C17/16

CPC classification number: G11C17/18 ,  G11C17/165

Abstract: A fuse-programmable register or memory location having a plurality of fusible links of differing electrical characteristics in parallel. In one embodiment, three fusible links with different resistances are provided, such that application of a programming voltage non-uniformly distributes the current among the links, allowing varying voltages to selectively blow one or more of the links. Sensing of the programmed state is performed by applying a voltage across the parallel links and measuring the current in comparison with a plurality of reference currents. Reduction in the overhead chip area per bit and in the serial data communication latency are obtained.

公开(公告)号：US20170018311A1

公开(公告)日：2017-01-19

申请号：US15146049

申请日：2016-05-04

Applicant: Texas Instruments Incorporated

Inventor： Sunil Kumar Dusa ,  Richard Allen Bailey ,  Archana Venugopal ,  John Anthony Rodriguez ,  Michael Allen Ball

IPC: G11C17/18 ,  G11C17/16

CPC classification number: G11C17/18 ,  G11C17/165

Abstract: A fuse-programmable register or memory location having a plurality of fusible links of differing electrical characteristics in parallel. In one embodiment, three fusible links with different resistances are provided, such that application of a programming voltage non-uniformly distributes the current among the links, allowing varying voltages to selectively blow one or more of the links. Sensing of the programmed state is performed by applying a voltage across the parallel links and measuring the current in comparison with a plurality of reference currents. Reduction in the overhead chip area per bit and in the serial data communication latency are obtained.

Abstract translation: 熔丝可编程寄存器或存储器位置具有并联的具有不同电特性的多个可熔链路。 在一个实施例中，提供具有不同电阻的三个可熔链路，使得编程电压的施加不均匀地分布在链路之间的电流，允许变化的电压选择性地吹送一个或多个链路。 通过跨多个并联链路施加电压并且与多个参考电流相比测量电流来执行编程状态的感测。 获得每位开销芯片面积的减少和串行数据通信延迟。

公开(公告)号：US20160086960A1

公开(公告)日：2016-03-24

申请号：US14728683

申请日：2015-06-02

Applicant: Texas Instruments Incorporated

Inventor： Huang-Chun Wen ,  Richard Allen Bailey ,  Antonio Guillermo Acosta ,  John A. Rodriguez ,  Scott Robert Summerfelt ,  Kemal Tamer San

IPC: H01L27/115 ,  H01L21/02 ,  H01L29/78 ,  H01L23/31 ,  H01L23/29 ,  H01L21/326 ,  H01L23/00

CPC classification number: H01L27/11507 ,  H01L21/02118 ,  H01L21/0217 ,  H01L21/02197 ,  H01L21/02318 ,  H01L21/56 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/562 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2924/07025 ,  H01L2924/014

Abstract: Curing of a passivation layer applied to the surface of a ferroelectric integrated circuit so as to enhance the polarization characteristics of the ferroelectric structures. A passivation layer, such as a polyimide, is applied to the surface of the ferroelectric integrated circuit after fabrication of the active devices. The passivation layer is cured by exposure to a high temperature, below the Curie temperature of the ferroelectric material, for a short duration such as on the order of ten minutes. Variable frequency microwave energy may be used to effect such curing. The cured passivation layer attains a tensile stress state, and as a result imparts a compressive stress upon the underlying ferroelectric material. Polarization may be further enhanced by polarizing the ferroelectric material prior to the cure process.

Abstract translation: 固化施加到铁电集成电路的表面的钝化层，以增强铁电结构的极化特性。 在制造有源器件之后，将钝化层（例如聚酰亚胺）施加到铁电集成电路的表面。 钝化层通过暴露于低于铁电材料的居里温度的高温固化，持续时间短，例如十分钟左右。 可以使用变频微波能量来实现这种固化。 固化的钝化层达到拉伸应力状态，结果赋予了下伏的铁电材料的压应力。 在固化过程之前极化铁电材料可以进一步提高极化。