公开(公告)号：US20220358980A1

公开(公告)日：2022-11-10

申请号：US17871983

申请日：2022-07-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY

Inventor： Zong-You LUO ,  Ya-Jui TSOU ,  Chee-Wee LIU ,  Shao-Yu LIN ,  Liang-Chor CHUNG ,  Chih-Lin WANG

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/12 ,  H01L43/08 ,  H01L43/10 ,  H01L43/02

Abstract: A method includes forming bottom conductive lines over a wafer. A first magnetic tunnel junction (MTJ) stack is formed over the bottom conductive lines. Middle conductive lines are formed over the first MTJ stack. A second MTJ stack is formed over the middle conductive lines. Top conductive lines are formed over the second MTJ stack.

公开(公告)号：US20210225765A1

公开(公告)日：2021-07-22

申请号：US17226963

申请日：2021-04-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Zhi-Sheng ZHENG ,  Chih-Lin WANG

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532 ,  H01L23/528

Abstract: A device comprises a first dielectric layer, a first conductor, a carbon-containing etch stop layer, a second dielectric layer, and a second conductor. The first conductor has a lower portion in the first dielectric layer. The carbon-containing etch stop layer wraps an upper portion of the first conductor. The second dielectric layer is over the carbon-containing etch stop layer. An interface formed by the second dielectric layer and the carbon-containing etch stop layer is higher over the first conductor than over the first dielectric layer. The second conductor is in the second dielectric layer.

公开(公告)号：US20180197969A1

公开(公告)日：2018-07-12

申请号：US15911884

申请日：2018-03-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Ruei YEH ,  Chih-Lin WANG ,  Kang-Min KUO

IPC: H01L29/51 ,  H01L29/78 ,  H01L29/45 ,  H01L29/423 ,  H01L21/02 ,  H01L21/768 ,  H01L29/40

CPC classification number: H01L29/518 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76855 ,  H01L23/485 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/45 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/7848

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a metal gate electrode structure and an insulating layer over the semiconductor substrate. The insulating layer surrounds the metal gate electrode structure. The method includes nitrifying a first top portion of the metal gate electrode structure to form a metal nitride layer over the metal gate electrode structure.

公开(公告)号：US20180158727A1

公开(公告)日：2018-06-07

申请号：US15888999

申请日：2018-02-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wen-Jia HSIEH ,  Long-Jie HONG ,  Chih-Lin WANG ,  Kang-Min KUO

IPC: H01L21/768 ,  H01L21/285 ,  H01L21/311 ,  H01L29/161 ,  H01L29/45 ,  H01L23/485 ,  H01L29/16 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L23/532

Abstract: The semiconductor device includes a substrate, an epi-layer, a first etch stop layer, an interlayer dielectric (ILD) layer, a second etch stop layer, a protective layer, a liner, a silicide cap and a contact plug. The substrate has a first portion and a second portion. The epi-layer is disposed in the first portion. The first etch stop layer is disposed on the second portion. The ILD layer is disposed on the first etch stop layer. The second etch stop layer is disposed on the ILD layer, in which the first etch stop layer, the ILD layer and the second etch stop layer form a sidewall surrounding the first portion. The protective layer is disposed on the sidewall. The liner is disposed on the protective layer. The silicide cap is disposed on the epi-layer. The contact plug is disposed on the silicide cap and surrounded by the liner.

公开(公告)号：US20150340475A1

公开(公告)日：2015-11-26

申请号：US14819654

申请日：2015-08-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chien-Chih LIN ,  Long-Jie HONG ,  Chih-Lin WANG ,  Chia-Der CHANG

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/3105 ,  H01L21/311

CPC classification number: H01L29/66795 ,  H01L21/31055 ,  H01L21/311 ,  H01L21/31144 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785

Abstract: A method for manufacturing a semiconductor device includes forming two isolation structures in a substrate to define a fin structure between the two isolation structures in the substrate. A dummy gate and spacers are formed bridging the two isolation structures and over the fin structure. The two isolation structures are etched with the dummy gate and the spacers as a mask to form a plurality of slopes under the spacers in the two isolation structures. A gate etch stop layer is formed overlying the plurality of slopes. The dummy gate and the two isolation structures beneath the dummy gate are removed to create a cavity confined by the spacers and the gate etch stop layer. A gate is then formed in the cavity.

Abstract translation: 一种用于制造半导体器件的方法包括在衬底中形成两个隔离结构以在衬底中的两个隔离结构之间限定翅片结构。 形成虚拟栅极和间隔物，桥接两个隔离结构和鳍状结构。 用虚拟栅极和间隔物作为掩模蚀刻两个隔离结构，以在两个隔离结构中的间隔物下方形成多个斜面。 在多个斜面上形成栅极蚀刻停止层。 去除虚拟栅极和虚拟栅极之下的两个隔离结构以产生由间隔物和栅极蚀刻停止层限制的空腔。 然后在空腔中形成栅极。

公开(公告)号：US20230363287A1

公开(公告)日：2023-11-09

申请号：US18353569

申请日：2023-07-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY

Inventor： Ya-Jui TSOU ,  Zong-You LUO ,  Chee-Wee LIU ,  Shao-Yu LIN ,  Liang-Chor CHUNG ,  Chih-Lin WANG

IPC: H10N50/80 ,  G11C11/16 ,  H10B61/00 ,  H10N50/01

CPC classification number: H10N50/80 ,  G11C11/161 ,  H10B61/00 ,  H10N50/01

Abstract: A method includes forming a memory stack over a substrate. A dielectric layer is deposited to cover the memory stack. An opening is formed in the dielectric layer. The opening does not expose the memory stack. A spin-orbit-torque (SOT) layer is formed in the opening. A free layer is formed over the dielectric layer to interconnect the memory stack and the SOT layer.

公开(公告)号：US20170098605A1

公开(公告)日：2017-04-06

申请号：US15379461

申请日：2016-12-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Zhi-Sheng ZHENG ,  Chih-Lin WANG

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76883 ,  H01L21/76885 ,  H01L23/5283 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interconnection structure includes a first dielectric layer, at least one first conductor, and an etch stop layer. The first conductor is disposed partially in the first dielectric layer and has a portion protruding from the first dielectric layer. The etch stop layer is disposed on the first dielectric layer and covers the protruding portion of the first conductor. The etch stop layer has a cap portion on a top surface of the protruding portion of the first conductor and a spacer portion on at least one sidewall of the protruding portion of the first conductor, and the spacer portion is thicker than the cap portion.

公开(公告)号：US20170053868A1

公开(公告)日：2017-02-23

申请号：US14832655

申请日：2015-08-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shu-Cheng LIN ,  Chih-Lin WANG ,  Kang-Min KUO

IPC: H01L23/522 ,  H01L21/02 ,  H01L23/532 ,  H01L21/311 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L21/76877 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76831 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first conductive structure over the substrate. The semiconductor device structure includes a first dielectric layer over the substrate. The first dielectric layer has a first opening exposing the first conductive structure. The semiconductor device structure includes a seal layer covering an inner wall of the first opening and in direct contact with the first dielectric layer. The seal layer includes a dielectric material including an oxygen compound. The semiconductor device structure includes a second conductive structure filled in the first opening and surrounded by the seal layer. The second conductive structure is electrically connected to the first conductive structure.

Abstract translation: 提供半导体器件结构。 半导体器件结构包括衬底。 半导体器件结构包括在衬底上的第一导电结构。 半导体器件结构包括在衬底上的第一介电层。 第一电介质层具有暴露第一导电结构的第一开口。 半导体器件结构包括覆盖第一开口的内壁并与第一介电层直接接触的密封层。 密封层包括包含氧化合物的电介质材料。 半导体器件结构包括填充在第一开口中并被密封层包围的第二导电结构。 第二导电结构电连接到第一导电结构。

公开(公告)号：US20160190062A1

公开(公告)日：2016-06-30

申请号：US14850848

申请日：2015-09-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Zhi-Sheng ZHENG ,  Chih-Lin WANG

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76883 ,  H01L21/76885 ,  H01L23/5283 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interconnection structure includes a first dielectric layer, a first conductor, an etch stop layer, a second dielectric layer, and a second conductor. The first dielectric layer has at least one hole therein. The first conductor is disposed at least partially in the hole of the first dielectric layer. The etch stop layer is disposed on the first dielectric layer. The etch stop layer has an opening to at least partially expose the first conductor. The second dielectric layer is disposed on the etch stop layer and has at least one hole therein. The hole of the second dielectric layer is in communication with the opening of the etch stop layer. The second conductor is disposed at least partially in the hole of the second dielectric layer and is electrically connected to the first conductor through the opening of the etch stop layer.

Abstract translation: 互连结构包括第一介电层，第一导体，蚀刻停止层，第二介电层和第二导体。 第一电介质层中至少有一个孔。 第一导体至少部分地设置在第一介电层的孔中。 蚀刻停止层设置在第一介电层上。 蚀刻停止层具有至少部分地暴露第一导体的开口。 第二介电层设置在蚀刻停止层上并且在其中具有至少一个孔。 第二电介质层的孔与蚀刻停止层的开口连通。 第二导体至少部分地设置在第二电介质层的孔中，并且通过蚀刻停止层的开口与第一导体电连接。

公开(公告)号：US20150228763A1

公开(公告)日：2015-08-13

申请号：US14176873

申请日：2014-02-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chien-Chih LIN ,  Long-Jie HONG ,  Chih-Lin WANG ,  Chia-Der CHANG

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/311 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/31055 ,  H01L21/311 ,  H01L21/31144 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785

Abstract: A method for manufacturing a semiconductor device includes forming two isolation structures in a substrate to define a fin structure between the two isolation structures in the substrate. A dummy gate and spacers are formed bridging the two isolation structures and over the fin structure. The two isolation structures are etched with the dummy gate and the spacers as a mask to form a plurality of slopes under the spacers in the two isolation structures. A gate etch stop layer is formed overlying the plurality of slopes. The dummy gate and the two isolation structures beneath the dummy gate are removed to create a cavity confined by the spacers and the gate etch stop layer. A gate is then formed in the cavity.

Abstract translation: 一种用于制造半导体器件的方法包括在衬底中形成两个隔离结构以在衬底中的两个隔离结构之间限定翅片结构。 形成虚拟栅极和间隔物，桥接两个隔离结构和鳍状结构。 用虚拟栅极和间隔物作为掩模蚀刻两个隔离结构，以在两个隔离结构中的间隔物下方形成多个斜面。 在多个斜面上形成栅极蚀刻停止层。 去除虚拟栅极和虚拟栅极之下的两个隔离结构以产生由间隔物和栅极蚀刻停止层限制的空腔。 然后在空腔中形成栅极。