公开(公告)号：US20200350404A1

公开(公告)日：2020-11-05

申请号：US16932924

申请日：2020-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun Hsiung Tsai ,  Wei-Yuan Lu ,  Chien-Tai Chan ,  Wei-Yang Lee ,  Da-Wen Lin

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/02 ,  H01L29/16 ,  H01L29/32 ,  H01L29/04 ,  H01L29/06 ,  H01L29/165

Abstract: Embodiments of mechanisms for forming dislocations in source and drain regions of finFET devices are provided. The mechanisms involve recessing fins and removing the dielectric material in the isolation structures neighboring fins to increase epitaxial regions for dislocation formation. The mechanisms also involve performing a pre-amorphous implantation (PAI) process either before or after the epitaxial growth in the recessed source and drain regions. An anneal process after the PAI process enables consistent growth of the dislocations in the source and drain regions. The dislocations in the source and drain regions (or stressor regions) can form consistently to produce targeted strain in the source and drain regions to improve carrier mobility and device performance for NMOS devices.

公开(公告)号：US10468500B1

公开(公告)日：2019-11-05

申请号：US16024506

申请日：2018-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun Hsiung Tsai ,  Cheng-Yi Peng ,  Yin-Pin Wang ,  Kuo-Feng Yu ,  Da-Wen Lin ,  Jian-Hao Chen ,  Shahaji B. More

IPC: H01L29/66 ,  H01L21/265 ,  H01L21/324 ,  H01L21/768 ,  H01L21/223 ,  H01L21/8234

Abstract: A method and structure for doping source and drain (S/D) regions of a PMOS and/or NMOS FinFET device are provided. In some embodiments, a method includes providing a substrate including a fin extending therefrom. In some examples, the fin includes a channel region, source/drain regions disposed adjacent to and on either side of the channel region, a gate structure disposed over the channel region, and a main spacer disposed on sidewalls of the gate structure. In some embodiments, contact openings are formed to provide access to the source/drain regions, where the forming the contact openings may etch a portion of the main spacer. After forming the contact openings, a spacer deposition and etch process may be performed. In some cases, after performing the spacer deposition and etch process, a silicide layer is formed over, and in contact with, the source/drain regions.

公开(公告)号：US20240379802A1

公开(公告)日：2024-11-14

申请号：US18783194

申请日：2024-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Lin Lee ,  Choh Fei Yeap ,  Da-Wen Lin ,  Chih Yeh

IPC: H01L29/423 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/786

Abstract: A first gate-all-around (GAA) transistor is formed on the first fin structure; the first GAA transistor has a channel region within a first plurality of nanostructures. A second GAA transistor is formed on the second fin structure; the second GAA transistor has a second channel region configuration. The second GAA transistor has a channel region within a second plurality of nanostructures. The second plurality of nanostructures is less than the first plurality of nanostructures.

公开(公告)号：US11742400B2

公开(公告)日：2023-08-29

申请号：US16432594

申请日：2019-06-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting Fang ,  Da-Wen Lin ,  Fu-Kai Yang ,  Chen-Ming Lee ,  Mei-Yun Wang

IPC: H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L29/45

CPC classification number: H01L29/423 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/456 ,  H01L29/66795 ,  H01L29/785

Abstract: A FinFET device structure and method for forming the same is provided. The FinFET device structure includes an isolation structure formed over a substrate, and a gate structure formed over the isolation structure. The FinFET device structure includes a first dielectric layer formed over the isolation structure and adjacent to the gate structure and a source/drain (S/D) contact structure formed in the first dielectric layer. The FinFET device structure also includes a deep contact structure formed through the first dielectric layer and adjacent to the S/D contact structure. The deep contact structure is through the isolation structure, and a bottom surface of the S/D contact structure is higher than a bottom surface of the deep contact structure.

公开(公告)号：US20220285513A1

公开(公告)日：2022-09-08

申请号：US17465665

申请日：2021-09-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Yeh Chen ,  Wei-Yang Lee ,  Chia-Pin Lin ,  Da-Wen Lin

IPC: H01L29/423 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/786 ,  H01L29/66

Abstract: Gate spacer that improves performance and methods for fabricating such are disclosed herein. An exemplary device includes a gate stack disposed over a semiconductor layer and a gate spacer disposed on a sidewall of the gate stack. A source/drain feature is disposed in the semiconductor layer and adjacent the gate spacer. A low-k contact etch stop layer is disposed on a top surface and a sidewall of the gate spacer and a portion of the gate spacer is disposed between the low-k contact etch stop layer and the semiconductor layer. A source/drain contact is disposed on the source/drain feature and adjacent the low-k contact etch stop layer.

公开(公告)号：US11211455B2

公开(公告)日：2021-12-28

申请号：US16932924

申请日：2020-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun Hsiung Tsai ,  Wei-Yuan Lu ,  Chien-Tai Chan ,  Wei-Yang Lee ,  Da-Wen Lin

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/02 ,  H01L29/16 ,  H01L29/32 ,  H01L29/04 ,  H01L29/06 ,  H01L29/165

Abstract: Embodiments of mechanisms for forming dislocations in source and drain regions of finFET devices are provided. The mechanisms involve recessing fins and removing the dielectric material in the isolation structures neighboring fins to increase epitaxial regions for dislocation formation. The mechanisms also involve performing a pre-amorphous implantation (PAI) process either before or after the epitaxial growth in the recessed source and drain regions. An anneal process after the PAI process enables consistent growth of the dislocations in the source and drain regions. The dislocations in the source and drain regions (or stressor regions) can form consistently to produce targeted strain in the source and drain regions to improve carrier mobility and device performance for NMOS devices.

公开(公告)号：US10522417B2

公开(公告)日：2019-12-31

申请号：US15725544

申请日：2017-10-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Lung Cheng ,  Yen-Chun Lin ,  Da-Wen Lin

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L21/02 ,  H01L21/311

Abstract: A semiconductor device includes a P-type Field Effect Transistor (PFET) and an NFET. The PFET includes an N-well disposed in a substrate, a first fin structure disposed over the N-well, a first liner layer disposed over the N-well, and a second liner layer disposed over the first liner layer. The first liner layer and the second liner layer include different materials. The NFET includes a P-well disposed in the substrate, a second fin structure disposed over the P-well, a third liner layer disposed over the P-well. The third liner layer and the second liner layer include the same materials.

公开(公告)号：US20180350697A1

公开(公告)日：2018-12-06

申请号：US16045992

申请日：2018-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Lung Cheng ,  Yen-Chun Lin ,  Da-Wen Lin

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/02 ,  H01L21/311 ,  H01L29/78

CPC classification number: H01L21/823821 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/31105 ,  H01L21/31144 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0924 ,  H01L27/0928 ,  H01L29/7843

Abstract: A semiconductor device includes a P-type Field Effect Transistor (PFET) and an NFET. The PFET includes an N-well disposed in a substrate, a first fin structure disposed over the N-well, a first liner layer disposed over the N-well, and a second liner layer disposed over the first liner layer. The first liner layer and the second liner layer include different materials. The NFET includes a P-well disposed in the substrate, a second fin structure disposed over the P-well, a third liner layer disposed over the P-well. The third liner layer and the second liner layer include the same materials.

公开(公告)号：US12125889B2

公开(公告)日：2024-10-22

申请号：US17465665

申请日：2021-09-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Yeh Chen ,  Wei-Yang Lee ,  Chia-Pin Lin ,  Da-Wen Lin

IPC: H01L29/423 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L21/823418 ,  H01L21/823468 ,  H01L29/0665 ,  H01L29/6656 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: Gate spacer that improves performance and methods for fabricating such are disclosed herein. An exemplary device includes a gate stack disposed over a semiconductor layer and a gate spacer disposed on a sidewall of the gate stack. A source/drain feature is disposed in the semiconductor layer and adjacent the gate spacer. A low-k contact etch stop layer is disposed on a top surface and a sidewall of the gate spacer and a portion of the gate spacer is disposed between the low-k contact etch stop layer and the semiconductor layer. A source/drain contact is disposed on the source/drain feature and adjacent the low-k contact etch stop layer.

公开(公告)号：US12068392B2

公开(公告)日：2024-08-20

申请号：US17654807

申请日：2022-03-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun Hsiung Tsai ,  Cheng-Yi Peng ,  Yin-Pin Wang ,  Kuo-Feng Yu ,  Da-Wen Lin ,  Jian-Hao Chen ,  Shahaji B. More

IPC: H01L29/66 ,  H01L21/223 ,  H01L21/265 ,  H01L21/324 ,  H01L21/768 ,  H01L21/8234

CPC classification number: H01L29/665 ,  H01L21/2236 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/324 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76825 ,  H01L21/76831 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/66515 ,  H01L29/66795

Abstract: A method and structure for doping source and drain (S/D) regions of a PMOS and/or NMOS FinFET device are provided. In some embodiments, a method includes providing a substrate including a fin extending therefrom. In some examples, the fin includes a channel region, source/drain regions disposed adjacent to and on either side of the channel region, a gate structure disposed over the channel region, and a main spacer disposed on sidewalls of the gate structure. In some embodiments, contact openings are formed to provide access to the source/drain regions, where the forming the contact openings may etch a portion of the main spacer. After forming the contact openings, a spacer deposition and etch process may be performed. In some cases, after performing the spacer deposition and etch process, a silicide layer is formed over, and in contact with, the source/drain regions.