公开(公告)号：US12217782B2

公开(公告)日：2025-02-04

申请号：US18332674

申请日：2023-06-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Gaurav Gupta ,  Zhiqiang Wu ,  Yih Wang

IPC: G11C11/16

Abstract: The disclosed MTJ read circuits include a current steering element coupled to the read path. At a first node of the current steering element, a proportionally larger current is maintained to meet the requirements of a reliable voltage or current sensing. At a second node of the current steering element, a proportionally smaller current is maintained, which passes through the MTJ structure. The current at the first node is proportional to the current at the second node such that sensing the current at the first node infers the current at the second node, which is affected by the MTJ resistance value.

公开(公告)号：US11955201B2

公开(公告)日：2024-04-09

申请号：US17873692

申请日：2022-07-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Sheng Chang ,  Chia-En Huang ,  Yi-Ching Liu ,  Yih Wang

IPC: G11C7/10 ,  G11C7/12 ,  G11C7/18 ,  G11C8/08 ,  G11C8/14

CPC classification number: G11C7/1051 ,  G11C7/1006 ,  G11C7/12 ,  G11C7/18 ,  G11C8/08 ,  G11C8/14

Abstract: A memory device includes a plurality of arrays coupled in parallel with each other. A first array of the plurality of arrays includes a first switch and a plurality of first memory cells that are arranged in a first column, a second switch and a plurality of second memory cells that are arranged in a second column, and at least one data line coupled to the plurality of first memory cells and the plurality of second memory cells. The second switch is configured to output a data signal from the at least one data line to a sense amplifier.

公开(公告)号：US11948972B2

公开(公告)日：2024-04-02

申请号：US16916951

申请日：2020-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Xuan Huang ,  Chia-En Huang ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Yih Wang

IPC: H01L29/06 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H10B20/20

CPC classification number: H01L29/0673 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/785 ,  H10B20/20

Abstract: The present disclosure is directed to methods for the formation of high-voltage nano-sheet transistors and low-voltage gate-all-around transistors on a common substrate. The method includes forming a fin structure with first and second nano-sheet layers on the substrate. The method also includes forming a gate structure having a first dielectric and a first gate electrode on the fin structure and removing portions of the fin structure not covered by the gate structure. The method further includes partially etching exposed surfaces of the first nano-sheet layers to form recessed portions of the first nano-sheet layers in the fin structure and forming a spacer structure on the recessed portions. In addition, the method includes replacing the first gate electrode with a second dielectric and a second gate electrode, and forming an epitaxial structure abutting the fin structure.

公开(公告)号：US11681468B2

公开(公告)日：2023-06-20

申请号：US16985240

申请日：2020-08-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hiroki Noguchi ,  Shih-Lien Linus Lu ,  Yu-Der Chih ,  Yih Wang

IPC: G06F3/06 ,  G06F9/48 ,  G06F1/28

CPC classification number: G06F3/0659 ,  G06F1/28 ,  G06F3/0604 ,  G06F3/0673 ,  G06F9/4893

Abstract: A memory device including a memory array with a plurality of memory macros, a power supplying circuit, and a controller is provided. The power supplying circuit is coupled to the memory array. The controller is coupled to the memory array. The power supplying circuit is configured to provide power to perform write operations to a number of the memory macros at the same time. The number of the memory macros for the write operations performed at the same time is not higher than a maximum number of the memory macros. The controller obtains the maximum number of the memory macros for the write operations performed at the same time by the power supplying circuit. The controller re-arranges a schedule for a sequence of the write operations of the memory macros to generate a re-arranged schedule. The maximum number is taken as a threshold value. In the re-arranged schedule, a number of part of the memory macros for the write operations performed at the same time is equal to or less then the threshold value.

公开(公告)号：US20220215869A1

公开(公告)日：2022-07-07

申请号：US17703869

申请日：2022-03-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Gaurav Gupta ,  Zhiqiang Wu ,  Yih Wang

IPC: G11C11/16

Abstract: The disclosed MTJ read circuits include a current steering element coupled to the read path. At a first node of the current steering element, a proportionally larger current is maintained to meet the requirements of a reliable voltage or current sensing. At a second node of the current steering element, a proportionally smaller current is maintained, which passes through the MTJ structure. The current at the first node is proportional to the current at the second node such that sensing the current at the first node infers the current at the second node, which is affected by the MTJ resistance value.

公开(公告)号：US11322680B2

公开(公告)日：2022-05-03

申请号：US16884297

申请日：2020-05-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Perng-Fei Yuh ,  Yih Wang

IPC: G11C11/16 ,  H01L43/02 ,  G11C5/02 ,  H01L27/22

Abstract: Magnetic random access memory (MRAM) cells are provided. An MRAM cell includes a plurality of stacked magnetic tunnel junction (MTJ) devices coupled in serial and a transistor. The transistor having a gate coupled to a word line, a first terminal coupled to a bit line through the stacked MTJ devices, and a second terminal coupled to a source line. The stacked MTJ devices are different sizes.

公开(公告)号：US11309005B2

公开(公告)日：2022-04-19

申请号：US16655056

申请日：2019-10-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Gaurav Gupta ,  Zhiqiang Wu ,  Yih Wang

IPC: G11C11/00 ,  G11C11/16

Abstract: The disclosed MTJ read circuits include a current steering element coupled to the read path. At a first node of the current steering element, a proportionally larger current is maintained to meet the requirements of a reliable voltage or current sensing. At a second node of the current steering element, a proportionally smaller current is maintained, which passes through the MTJ structure. The current at the first node is proportional to the current at the second node such that sensing the current at the first node infers the current at the second node, which is affected by the MTJ resistance value.

公开(公告)号：US10978144B2

公开(公告)日：2021-04-13

申请号：US16572625

申请日：2019-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-En Huang ,  Hidehiro Fujiwara ,  Jui-Che Tsai ,  Yen-Huei Chen ,  Yih Wang

IPC: G11C7/00 ,  G11C11/419 ,  H01L27/11 ,  G11C5/06 ,  G11C11/418

Abstract: An integrated circuit and an operating method thereof are provided. The integrated circuit includes memory cells, at least one first word line, second word lines, bit lines and write-assist bit lines. The at least one first word line is electrically connected to at least one row of the memory cells. The second word lines are electrically connected to other rows of the memory cells. Two bit lines are located between a column of the memory cells and two write-assist bit lines. The bit lines and the write-assist bit lines are configured to be electrically disconnected with each other when at least one of the memory cells electrically connected with the at least one first word line is configured to be written, and electrically connected with each other when at least one of the memory cells electrically connected to the second word lines is configured to be written.

公开(公告)号：US20210066319A1

公开(公告)日：2021-03-04

申请号：US16805868

申请日：2020-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Sheng Chang ,  Chia-En Huang ,  Yi-Hsun Chiu ,  Yih Wang

IPC: H01L27/112 ,  H01L23/525

Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes a transistor, a first embedded insulating structure and a second embedded insulating structure. The transistor is formed on a substrate, and includes a gate structure, channel structures, a source electrode and a drain electrode. The channel structures penetrate through the gate structure, and are in contact with the source and drain electrodes. The first and second embedded insulating structures are disposed in the substrate, and overlapped with the source and drain electrodes. The first and second embedded insulating structures are laterally spaced apart from each other by a portion of the substrate lying under the gate structure.

公开(公告)号：US12230359B2

公开(公告)日：2025-02-18

申请号：US18164282

申请日：2023-02-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Sheng Chang ,  Yao-Jen Yang ,  Yih Wang ,  Fu-An Wu

IPC: G11C7/10 ,  G11C5/06 ,  G11C8/08 ,  G11C17/16 ,  G11C17/18 ,  H01L23/522 ,  H01L23/525 ,  H10B20/25

Abstract: A semiconductor device includes anti-fuse cells. The anti-fuse cells include a first active area, a first gate, a second gate, at least one first gate via, and at least one second gate via. The first gate and the second gate are separate from each other. The first gate and the second gate extend to cross over the first active area. The at least one first gate via is coupled to the first gate and disposed directly above the first active area. The at least one second gate via is coupled to the second gate. The first gate is coupled through the at least one first gate via to a first word line for receiving a first programming voltage, and the second gate is coupled through the at least one second gate via to a second word line for receiving a first reading voltage.