公开(公告)号：US5793067A

公开(公告)日：1998-08-11

申请号：US675968

申请日：1996-07-05

申请人： Takeshi Miura ,  Teruyuki Shimura ,  Manabu Katoh

发明人： Takeshi Miura ,  Teruyuki Shimura ,  Manabu Katoh

IPC分类号： H01L23/495 ,  H01L25/07 ,  H01L31/0328

CPC分类号： H01L23/49562 ,  H01L23/49568 ,  H01L25/072 ,  H01L2924/0002

摘要： An electrode lead of a transistor extends beyond other electrode leads of the transistor, is disposed adjacent to the corresponding electrode, and is disposed outside the other electrode leads for heat radiation. A wider part of the electrode lead may have a via hole or a thick metal plating for heat radiation. Further, the electrode is preferably grounded and is connected to an external input terminal to which heat is transferred.

摘要翻译： 晶体管的电极引线延伸超过晶体管的其他电极引线，与相应的电极相邻设置，并且设置在另一个电极引线外部用于散热。 电极引线的较宽部分可以具有用于热辐射的通孔或厚金属电镀。 此外，电极优选地接地并且连接到热传递到的外部输入端子。

公开(公告)号：US5864169A

公开(公告)日：1999-01-26

申请号：US503952

申请日：1995-07-19

申请人： Teruyuki Shimura ,  Masayuki Sakai ,  Ryo Hattori ,  Hiroshi Matsuoka ,  Manabu Katoh

发明人： Teruyuki Shimura ,  Masayuki Sakai ,  Ryo Hattori ,  Hiroshi Matsuoka ,  Manabu Katoh

IPC分类号： H01L23/52 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/8222 ,  H01L23/367 ,  H01L23/48 ,  H01L23/522 ,  H01L23/538 ,  H01L27/082 ,  H01L31/0328 ,  H01L23/34

CPC分类号： H01L23/5381 ,  H01L21/76898 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/481 ,  H01L24/05 ,  H01L2224/04042 ,  H01L2224/48455 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/30107

摘要： A semiconductor device includes a semiconductor substrate having opposite front and rear surfaces; a semiconductor element disposed on the front surface of the semiconductor substrate and including an electrode; a PHS for dissipating heat generated in the semiconductor element, the PHS including a metal layer and disposed on the rear surface of the semiconductor substrate; a via-hole including a through-hole penetrating through the semiconductor substrate from the front surface to the rear surface and having an inner surface, and a metal disposed in the through-hole and contacting the PHS; and an air-bridge wiring including a metal film and having first and second portions, the air-bridge contacting the electrode of the semiconductor element at the first portion and contacting the metal of the via-hole at the second portion. Therefore, heat produced in the semiconductor element is transferred to the PHS not only through the semiconductor substrate just under the element but also through the air-bridge wiring and the via-hole, whereby the heat dissipating property of the device is significantly improved.

摘要翻译： 半导体器件包括具有相对的前表面和后表面的半导体衬底; 半导体元件，设置在所述半导体基板的前表面上并且包括电极; 用于散发在半导体元件中产生的热的PHS，PHS包括金属层并设置在半导体衬底的后表面上; 通孔，该通孔包括从前表面到后表面穿过半导体衬底的通孔，并具有内表面，以及设置在通孔中并与PHS接触的金属; 以及包括金属膜并具有第一和第二部分的空气桥接布线，所述空气桥接在所述第一部分处与所述半导体元件的电极接触并且在所述第二部分与所述通孔的金属接触。 因此，半导体元件中产生的热量不仅通过刚好在元件下方的半导体衬底传递到PHS，而且还通过气桥布线和通孔传递到PHS，从而显着提高了器件的散热性能。

公开(公告)号：US5719530A

公开(公告)日：1998-02-17

申请号：US634966

申请日：1996-04-19

申请人： Teruyuki Shimura ,  Manabu Katoh

发明人： Teruyuki Shimura ,  Manabu Katoh

IPC分类号： H01L21/331 ,  H01L23/66 ,  H01L29/73 ,  H03F3/60 ,  H03F3/68

CPC分类号： H01L23/66 ,  H01L29/73 ,  H01L2223/6644 ,  H01L2924/0002

摘要： A high power bipolar transistor includes bipolar transistors disposed on a substrate; a signal line including a pad for inputting a driving signal and a signal transmission line continuous with the pad commonly connecting base electrodes of the bipolar transistors; and a bypass line having a first end connected to the signal transmission line proximate to the pad and a second end connected to the signal transmission line remote from the pad. Approximately equal powers are supplied to the transistors connected to any position on the base feed line so that the operation of the respective transistors is uniform, improving output power and efficiency.

摘要翻译： 高功率双极晶体管包括设置在基板上的双极晶体管; 信号线，包括用于输入驱动信号的焊盘和与通常连接双极晶体管的基极的焊盘连续的信号传输线; 以及旁路管线，其具有连接到靠近焊盘的信号传输线的第一端和连接到远离焊盘的信号传输线的第二端。 大约相等的功率被提供给连接到基极馈电线上的任何位置的晶体管，使得各个晶体管的工作是均匀的，从而提高输出功率和效率。

公开(公告)号：US06861906B2

公开(公告)日：2005-03-01

申请号：US10204446

申请日：2001-05-11

申请人： Kazutomi Mori ,  Shintaro Shinjo ,  Kousei Maemura ,  Teruyuki Shimura ,  Kazuhiko Nakahara ,  Tadashi Takagi

发明人： Kazutomi Mori ,  Shintaro Shinjo ,  Kousei Maemura ,  Teruyuki Shimura ,  Kazuhiko Nakahara ,  Tadashi Takagi

IPC分类号： H01L27/06 ,  H03F3/19 ,  H03F3/21 ,  H03F3/68

CPC分类号： H01L27/0605 ,  H03F3/19 ,  H03F3/211 ,  H03F2203/21178

摘要： A high-frequency semiconductor device according to the present invention achieves improvements in degradation of noise characteristics and a reduction in gain, and an improvement in reduction in power efficiency while suppressing a concentration of a current to multifinger HBTs. In the multifinger HBTs constituting a first stage and an output stage of an amplifier 10, basic HBTs 14 that constitute the multifinger HBT 12 corresponding to the first stage, are each made up of an HBT 14a and an emitter resistor 14b connected to the corresponding emitter of the HBT 14a, whereas basic HBTs 18 that constitute the multifinger HBT 16 corresponding to the output stage, are each comprised of an HBT 18a and a base resistor 18c connected to the corresponding base of the HBT 18a. The high-frequency semiconductor device according to the present invention is useful as a high output power amplifier used in satellite communications, ground microwave communications, mobile communications, etc.

摘要翻译： 根据本发明的高频半导体器件实现了噪声特性的降低和增益的降低的改善，并且在抑制电流到多焦HBT的浓度的同时，提高了功率效率的降低。 在构成放大器10的第一级和输出级的多画面HBT中，构成对应于第一级的多画面HBT 12的基本HBT 14分别由连接到相应发射极的HBT 14a和发射极电阻14b组成 而构成与输出级相对应的多功能HBT16的基本HBT 18分别由连接到HBT 18a的相应基座的HBT 18a和基极电阻18c组成。 根据本发明的高频半导体器件可用作卫星通信，地面微波通信，移动通信等中使用的高输出功率放大器。

公开(公告)号：US5973543A

公开(公告)日：1999-10-26

申请号：US825220

申请日：1997-03-27

申请人： Teruyuki Shimura

发明人： Teruyuki Shimura

IPC分类号： H03F3/20 ,  G05F3/22 ,  H03F3/04 ,  G05F1/10

CPC分类号： G05F3/22

摘要： A bias circuit for a bipolar transistor includes a constant voltage source connected to a base electrode of the bipolar transistor; and a resistor connected in series between the constant voltage source and the base electrode of the bipolar transistor. By selecting an appropriate resistance for this resistor, the bias point moves due to a change in the voltage drop across the resistor. The change occurs because the base current flowing through the resistor changes, whereby the operating class of the transistor changes, resulting in a high efficiency at a desired output power.

摘要翻译： 用于双极晶体管的偏置电路包括连接到双极晶体管的基极的恒压源; 以及串联连接在双极晶体管的恒定电压源和基极之间的电阻器。 通过为该电阻选择合适的电阻，偏置点由于电阻上的电压降的变化而移动。 发生这种变化是因为流过电阻的基极电流发生变化，晶体管的工作类别发生变化，导致所需输出功率的效率高。

公开(公告)号：US4977100A

公开(公告)日：1990-12-11

申请号：US417288

申请日：1989-10-05

申请人： Teruyuki Shimura

发明人： Teruyuki Shimura

IPC分类号： H01L29/812 ,  H01L21/285 ,  H01L21/338 ,  H01L29/417 ,  H01L29/423

CPC分类号： H01L29/66878 ,  H01L21/28587 ,  H01L29/42316

摘要： A method of producing a MESFET which includes forming a refractory metal gate structure on an active layer formed in or on a semiconductor substrate. Source and drain regions optionally with extensions, are formed adjacent the gate structure. An insulating film is deposited over the partly formed structure to form a film portion on the semiconductor substrate which is separated from further film portions formed over the source and drain regions. A flattening resist is deposited over the insulating film and etched to expose only the film portion on the gate structure, while the gate structure itself and the resist protects the film portions on the source and drain regions. The film portion over the gate structure can thus be removed without damage to the gate structure or the remainder of the insulating film. The process produces with increased yield and more consistent properties in that the danger of attacking the refractory metal gate structure during operations succeeding its formation is significantly reduced.

摘要翻译： 一种MESFET的制造方法，其特征在于，在形成于半导体基板中的有源层上形成难熔金属栅极结构。 源极和漏极区域可选地具有延伸部分，邻近栅极结构形成。 在部分形成的结构上沉积绝缘膜，以在半导体衬底上形成薄膜部分，其与形成在源区和漏区上的其它膜部分分离。 平坦化抗蚀剂沉积在绝缘膜上并被蚀刻以仅暴露栅极结构上的膜部分，而栅极结构本身和抗蚀剂保护源极和漏极区域上的膜部分。 因此，能够去除栅极结构上的膜部分，而不会损坏栅极结构或绝缘膜的其余部分。 该方法产生具有增加的产量和更一致的性质，因为在其形成过程中的操作期间攻击难熔金属栅极结构的危险性显着降低。

公开(公告)号：US6081003A

公开(公告)日：2000-06-27

申请号：US985364

申请日：1997-12-04

申请人： Shinichi Miyakuni ,  Teruyuki Shimura

发明人： Shinichi Miyakuni ,  Teruyuki Shimura

IPC分类号： H01L29/73 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/331 ,  H01L29/08 ,  H01L29/205 ,  H01L29/737 ,  H01L31/072 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/109

CPC分类号： H01L29/66318 ,  H01L29/0817 ,  H01L29/7371

摘要： A heterojunction bipolar transistor is provided with a ballast resistor layer in an emitter layer which prevents the current amplification factor .beta. from decreasing. The n-GaAs carrier supply layer having a specified carrier concentration is formed between the ballast resistor layer and the n-AlGaAs layer.

摘要翻译： 异质结双极晶体管在发射极层中设置有镇流电阻层，防止电流放大因子β降低。 在镇流电阻层和n-AlGaAs层之间形成具有规定载流子浓度的n-GaAs载流子供给层。

公开(公告)号：US5192700A

公开(公告)日：1993-03-09

申请号：US828374

申请日：1992-01-30

申请人： Teruyuki Shimura

发明人： Teruyuki Shimura

IPC分类号： H01L21/265 ,  H01L21/337 ,  H01L21/338 ,  H01L21/76 ,  H01L27/095 ,  H01L29/778 ,  H01L29/80 ,  H01L29/808 ,  H01L29/812

CPC分类号： H01L29/66924 ,  H01L21/7605 ,  H01L29/802 ,  H01L29/808

摘要： A field effect transistor including a semi-insulating semiconductor substrate, a first conductivity type semiconductor layer disposed on the substrate and forming a heterojunction with the substrate, second conductivity type spaced apart source and drain regions extending through the layer into the substrate, a metallic gate disposed on the layer between the source and drain regions, and a second conductivity type channel disposed in the substrate extending between the source and drain regions and forming a pn heterojunction with the layer for reducing leakage current from the channel to the gate. The second conductivity type channel is produced by ion implantation, and the implantation conditions are controlled as a mechanism for controllably establishing a threshold voltage for the field effect transistor.

摘要翻译： 一种场效应晶体管，包括半绝缘半导体衬底，设置在衬底上并与衬底形成异质结的第一导电类型半导体层，延伸穿过衬底的第二导电类型间隔开的源极和漏极区，金属栅极 设置在源极和漏极区域之间的层上，以及第二导电类型沟道，设置在衬底中，在源极和漏极区域之间延伸，并且与该层形成pn异质结，以减少从沟道到栅极的泄漏电流。 通过离子注入产生第二导电类型沟道，并且将注入条件作为用于可控地建立场效应晶体管的阈值电压的机制来控制。

公开(公告)号：US5073812A

公开(公告)日：1991-12-17

申请号：US481619

申请日：1990-02-20

申请人： Teruyuki Shimura

发明人： Teruyuki Shimura

IPC分类号： H01L29/73 ,  H01L21/033 ,  H01L21/331 ,  H01L29/205 ,  H01L29/737

CPC分类号： H01L29/66318 ,  H01L21/033

摘要： A semiconductor device includes an n.sup.+ type InGaAs layer at a surface of the device, a refractory metal emitter electrode making ohmic contact to the n.sup.+ layer without alloying, and an externally accessible base region produced in the neighborhood of the emitter electrode by a diffusion using the emitter electrode and an insulating side wall film as a diffusion mask.

摘要翻译： 半导体器件在器件的表面包括n +型InGaAs层，难熔金属发射极电极，其在没有合金化的情况下与n +层形成欧姆接触，并且通过扩散使用在发射极附近产生的外部可接近的基极区域 发射电极和绝缘侧壁膜作为扩散掩模。

公开(公告)号：US4967254A

公开(公告)日：1990-10-30

申请号：US217292

申请日：1988-07-11

申请人： Teruyuki Shimura

发明人： Teruyuki Shimura

IPC分类号： H01L29/08

CPC分类号： H01L29/0804 ,  Y10S148/111

摘要： A semiconductor device includes a collector layer comprising a first conductivity type semiconductor layer, a base layer comprising a second conductivity type semiconductor layer produced on the collector layer, an emitter layer comprising a first conductivity type semiconductor layer produced on the base layer, a contact layer comprising an undoped semiconductor layer produced on the emitter layer, second conductivity type first implantation regions produced at regions each consisting of the contact layer, the emitter layer, and the base layer, so as to leave a central region therebetween, base electrodes produced on the first implantation regions, a first conductivity type second implantation region produced by implanting impurities from the surface of the contact layer extending into the emitter layer, in a region between the first implantation regions, and an emitter electrode produced on the second implantation region. Or, a semiconductor device includes an emitter layer comprising undoped semiconductor layer and a first conductivity type second implantation region produced by implanting impurities from the surface of the undoped semiconductor layer extending into the base layer, at a region between the first implantation regions.

摘要翻译： 半导体器件包括：集电极层，包括第一导电类型半导体层;基底层，包括在集电极层上制造的第二导电类型半导体层;发射极层，包括在基底层上制造的第一导电型半导体层;接触层 包括在发射极层上产生的未掺杂的半导体层，在由接触层，发射极层和基极层组成的区域处产生的第二导电类型的第一注入区域，以在其间留下中心区域，在 第一注入区域，通过从在第一注入区域之间的区域中延伸到发射极层的接触层的表面注入杂质而产生的第一导电类型的第二注入区域和在第二注入区域上产生的发射极。 或者，半导体器件包括发射极层，其包括未掺杂半导体层和通过在第一注入区域之间的区域处从未掺杂的半导体层的表面注入杂质而产生的第一导电类型的第二注入区域。