公开(公告)号：US5231311A

公开(公告)日：1993-07-27

申请号：US710838

申请日：1991-06-03

申请人： Thomas V. Ferry ,  Jamil Kawa ,  Kerry M. Pierce ,  William G. Walker ,  Michael A. Zampaglione ,  James S. Hsue

发明人： Thomas V. Ferry ,  Jamil Kawa ,  Kerry M. Pierce ,  William G. Walker ,  Michael A. Zampaglione ,  James S. Hsue

IPC分类号： H03K19/003

CPC分类号： H03K19/00361

摘要： A buffer characterized by a pull-up network and a pull-down network which are both coupled between an input and an output of the buffer. Each of the networks include a number of switch elements which can be sequentially turned on or off by means of an RC network to provide slew-rate control for the buffer. Preferably, each of the networks are associated with diode bypass networks to reduce crowbar current. In operation, both the pull-up network and the pull-down network turn on slowly but turn off very quickly due to the diode bypass networks.

摘要翻译： 一种缓冲器，其特征在于上拉网络和下拉网络，两者都耦合在缓冲器的输入和输出之间。 每个网络包括多个开关元件，其可以通过RC网络被顺序地接通或断开，以为缓冲器提供压摆率控制。 优选地，每个网络与二极管旁路网络相关联，以减少撬动电流。 在运行中，上拉网络和下拉网络均缓慢启动，但由于二极管旁路网络，它们都很快关闭。

公开(公告)号：US5111075A

公开(公告)日：1992-05-05

申请号：US665385

申请日：1991-03-05

申请人： Thomas V. Ferry ,  Jamil Kawa ,  Kerry M. Pierce ,  William G. Walker ,  Michael A. Zampaglione

发明人： Thomas V. Ferry ,  Jamil Kawa ,  Kerry M. Pierce ,  William G. Walker ,  Michael A. Zampaglione

IPC分类号： H03K17/16 ,  H03K19/003 ,  H03K19/0175

CPC分类号： H03K19/00361

摘要： A buffer characterized by a pull-up network and a pull-down network which are both coupled between an input and an output of the buffer. Each of the networks include a number of switch elements which can be sequentially turned on or off by means of an RC network to provide slew-rate control for the buffer. Preferably, each of the networks are associated with diode bypass networks to reduce crowbar current. In operation, both the pull-up network and the pull-down network turn on slowly but turn off very quickly due to the diode bypass networks.

摘要翻译： 一种缓冲器，其特征在于上拉网络和下拉网络，两者都耦合在缓冲器的输入和输出之间。 每个网络包括多个开关元件，其可以通过RC网络被顺序地接通或断开，以为缓冲器提供压摆率控制。 优选地，每个网络与二极管旁路网络相关联，以减少撬动电流。 在运行中，上拉网络和下拉网络均缓慢启动，但由于二极管旁路网络，它们都很快关闭。

公开(公告)号：US5146306A

公开(公告)日：1992-09-08

申请号：US638629

申请日：1991-01-08

申请人： Thomas V. Ferry ,  Jamil Kawa ,  Kerry M. Pierce ,  William G. Walker ,  James S. Hsue

发明人： Thomas V. Ferry ,  Jamil Kawa ,  Kerry M. Pierce ,  William G. Walker ,  James S. Hsue

IPC分类号： H03K19/003

CPC分类号： H03K19/00361

摘要： Slew-rate control is implemented in input/output device structures where MOSFETs are employed to switch the output signal. These MOSFETs each have a substrate, an insulating layer adjacent to the substrate and a strip of semiconductor material separated from the substrate by the insulating layer. The strip of semiconductor material functions as the gate of the MOSFET. The strip of semiconductor material does not form a closed loop. One end of the strip of a first transistor is connected to one end of the strip of the second transistor. Thus, the gates of the two transistors are placed in series so that they are not switched on at the same time. A delay is thereby automatically introduced between the switching on of the two transistors. The delay is controlled by placing metal straps across selected transistor gates to effectively bypass the delays caused by the current propagating through the gates. Further control of the delay is gained by use of a feedback signal to increase or decrease the current in the gates.

摘要翻译： 在使用MOSFET来切换输出信号的输入/输出器件结构中实现压摆率控制。 这些MOSFET各自具有基板，与基板相邻的绝缘层和通过绝缘层与基板分离的半导体材料条。 半导体材料条作为MOSFET的栅极起作用。 半导体材料条不形成闭环。 第一晶体管的条的一端连接到第二晶体管的条的一端。 因此，两个晶体管的栅极被串联放置，使得它们不被同时接通。 因此在两个晶体管的接通之间自动引入延迟。 通过将金属带放置在选定的晶体管栅极上来有效地绕过由栅极传播的电流引起的延迟来控制延迟。 通过使用反馈信号来增加或减少门中的电流来获得延迟的进一步控制。

公开(公告)号：US20110095367A1

公开(公告)日：2011-04-28

申请号：US12605102

申请日：2009-10-23

申请人： Qing Su ,  Min Ni ,  Zongwu Tang ,  Jamil Kawa ,  James D. Sproch

发明人： Qing Su ,  Min Ni ,  Zongwu Tang ,  Jamil Kawa ,  James D. Sproch

IPC分类号： H01L27/06 ,  G06F17/50 ,  H01L21/336

CPC分类号： G06F17/5068 ,  H01L23/481 ,  H01L23/60 ,  H01L23/62 ,  H01L27/0207 ,  H01L27/0255 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

摘要： Roughly described, an antenna diode is formed at least partially within the exclusion zone around a TSV, and is connected to the TSV by way of a metal 1 layer conductor at the same time that the TSV is connected to either the gate poly or a diffusion region of one or more transistors placed outside the exclusion zone.

摘要翻译： 粗略地描述，天线二极管至少部分地形成在TSV周围的排阻区内，并且通过金属1层导体连接到TSV，同时TSV连接到栅极多晶硅或扩散层 放置在排除区外的一个或多个晶体管的区域。

公开(公告)号：US07260807B2

公开(公告)日：2007-08-21

申请号：US10734399

申请日：2003-12-12

申请人： Narendra V. Shenoy ,  Jamil Kawa ,  Raul Camposano

发明人： Narendra V. Shenoy ,  Jamil Kawa ,  Raul Camposano

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F2217/64

摘要： One embodiment of the invention provides a system that facilitates designing an integrated circuit using a mask-programmable fabric, which contains both mask-programmable logic and a mask-programmable interconnect. During operation, the system receives a description of a mask-programmable cell, wherein instances of the mask-programmable cell are repeated to form the mask-programmable fabric. The system uses this description of the mask-programmable cell to generate a derived library containing cells that can be obtained by programming the mask-programmable cell. Next, the system receives a high-level design for the integrated circuit. The system then performs a synthesis operation on the high-level design to generate a preliminary netlist for the high-level design, wherein the preliminary netlist contains references to cells in the derived library. Finally, the system converts the preliminary netlist into a netlist that contains references to the mask-programmable cell with the logic appropriately programmed. The netlist is then placed and routed with the mask programmable constraints on the mask programmable fabric. The design, thus implemented on the programmable fabric, can be changed to accommodate logic revisions and bug fixes by changing only a few masks required for its fabrication.

摘要翻译： 本发明的一个实施例提供了一种使用包含掩模可编程逻辑和掩模可编程互连的掩码可编程结构来设计集成电路的系统。 在操作期间，系统接收掩模可编程单元的描述，其中重复掩模可编程单元的实例以形成掩模可编程结构。 该系统使用掩模可编程单元的描述来生成包含可通过对掩模可编程单元进行编程而获得的单元的导出库。 接下来，系统接收集成电路的高级设计。 然后，系统对高级设计执行合成操作，以生成高级设计的初步网表，其中初步网表包含对派生库中的单元的引用。 最后，系统将初步网表转换成网表，其中包含对具有适当编程逻辑的掩码可编程单元的引用。 然后将网表与面罩可编程织物上的掩码可编程约束放置和布线。 通过改变其制造所需的几个掩模，可以改变在可编程结构上实现的设计，以适应逻辑修订和错误修复。

公开(公告)号：US20050229141A1

公开(公告)日：2005-10-13

申请号：US10820523

申请日：2004-04-07

申请人： Jamil Kawa ,  Narendra Shenoy ,  Raul Camposano

发明人： Jamil Kawa ,  Narendra Shenoy ,  Raul Camposano

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： One embodiment of the invention provides a system for creating a mask-programmable module from standard cells. The system operates by first specifying characteristics of an end design and then selecting a plurality of standard cells from a standard cell library based on the characteristics of the end design. Next, the system combines the plurality of standard cells into a mask-programmable module, wherein instances of the mask-programmable module are repeated to form a mask-programmable fabric. The system also designs a mask-programmable interconnect to match the mask-programmable module, whereby connections within the mask-programmable module and between mask-programmable modules can be generated by programming the mask-programmable interconnect.

摘要翻译： 本发明的一个实施例提供了一种用于从标准单元创建掩模可编程模块的系统。 该系统通过首先指定终端设计的特征，然后基于终端设计的特征从标准小区库中选择多个标准小区来进行操作。 接下来，系统将多个标准单元组合成掩模可编程模块，其中重复掩模可编程模块的实例以形成掩模可编程结构。 该系统还设计了掩模可编程互连以匹配掩模可编程模块，从而可以通过对掩模可编程互连进行编程来生成掩模可编程模块内和掩模可编程模块之间的连接。

公开(公告)号：US09287253B2

公开(公告)日：2016-03-15

申请号：US13374335

申请日：2011-12-22

申请人： Victor Moroz ,  Jamil Kawa ,  James D. Sproch ,  Robert B. Lefferts

发明人： Victor Moroz ,  Jamil Kawa ,  James D. Sproch ,  Robert B. Lefferts

IPC分类号： H01L27/02 ,  H01L21/8238 ,  H01L27/092

CPC分类号： H01L27/0207 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0928

摘要： In one well bias arrangement, no well bias voltage is applied to the n-well, and no well bias voltage is applied to the p-well. Because no external well bias voltage is applied, the n-well and the p-well are floating, even during operation of the devices in the n-well and the p-well. In another well bias arrangement, the lowest available voltage is not applied to the p-well, such as a ground voltage, or the voltage applied to the n+-doped source region of the n-type transistor in the p-well. This occurs even during operation of the n-type transistor in the p-well. In yet another well bias arrangement, the highest available voltage is not applied to the n-well, such as a supply voltage, or the voltage applied to the p+-doped source region of the p-type transistor in the n-well. This occurs even during operation of the p-type transistor in the n-well.

公开(公告)号：US20140061936A1

公开(公告)日：2014-03-06

申请号：US13601394

申请日：2012-08-31

申请人： Victor Moroz ,  Jamil Kawa

发明人： Victor Moroz ,  Jamil Kawa

IPC分类号： H01L23/48 ,  G06F17/50 ,  H01L21/768

CPC分类号： H01L23/481 ,  H01L21/768 ,  H01L21/76898 ,  H01L23/48 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05548 ,  H01L2224/13024 ,  H01L2224/16238 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00

摘要： Roughly described, an integrated circuit device has a conductor extending entirely through the substrate, connected on one end to the substrate topside surface and on the other end to the substrate backside surface. In various embodiments the conductor is insulated from all RDL conductors on the backside of the substrate, and/or is insulated from all conductors and device features on any below-adjacent chip in a 3D integrated circuit structure. Methods of fabrication are also described.

公开(公告)号：US08561003B2

公开(公告)日：2013-10-15

申请号：US13194835

申请日：2011-07-29

申请人： Jamil Kawa ,  Victor Moroz ,  Deepak Sherlekar

发明人： Jamil Kawa ,  Victor Moroz ,  Deepak Sherlekar

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5077 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L2924/0002 ,  H01L2924/00

摘要： A finFET block architecture includes a first set of semiconductor fins having a first conductivity type, and a second set of semiconductor fins having a second conductivity type. An inter-block insulator is placed between outer fins of the first and second sets. A patterned gate conductor layer includes a first plurality of gate traces extending across the set of fins in the first block without crossing the inter-block insulator, and a second plurality of gate traces extending across the set of fins in the second block without crossing the inter-block insulator. Patterned conductor layers over the gate conductor layer are arranged in orthogonal layout patterns, and include an inter-block connector arranged to connect gate traces in the first and second blocks.

摘要翻译： finFET块结构包括具有第一导电类型的第一组半导体鳍片和具有第二导电类型的第二组半导体鳍片。 在第一和第二组的外部散热片之间放置一个块间绝缘体。 图案化栅极导体层包括跨越第一块中的翅片集合延伸的第一多个栅极迹线，而不跨越块间绝缘体;以及第二多个栅极迹线，跨越第二块中的翅片组延伸，而不会穿过第 块间​​绝缘体。 栅极导体层上的图案化导体层以正交布局图案布置，并且包括布置成连接第一和第二块中的栅极迹线的块间连接器。

公开(公告)号：US08176456B2

公开(公告)日：2012-05-08

申请号：US12343958

申请日：2008-12-24

申请人： Xin Wang ,  Charles C. Chiang ,  Jamil Kawa

发明人： Xin Wang ,  Charles C. Chiang ,  Jamil Kawa

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

摘要： One embodiment of the present invention provides a system that computes dummy feature density for a CMP (Chemical-Mechanical Polishing) process. Note that the dummy feature density is used to add dummy features to a layout to reduce the post-CMP topography variation. During operation, the system discretizes a layout of an integrated circuit into a plurality of panels. Next, the system computes a feature density and a slack density for the plurality of panels. The system then computes a dummy feature density for the plurality of panels by, iteratively, (a) calculating an effective feature density for the plurality of panels using the feature density and a function that models the CMP process, (b) calculating a filling amount for a set of panels in the plurality of panels using a target feature density, the effective feature density, and the slack density, and (c) updating the feature density, the slack density, and the dummy feature density for the set of panels using the filling amount. In one embodiment of the present invention, the iterative process is guided by a variance-minimizing heuristic to efficiently select the set of panels and assign/remove dummy density to the set of panels to decrease the effective feature density variation.

摘要翻译： 本发明的一个实施例提供了一种计算CMP（化学机械抛光）工艺的虚拟特征密度的系统。 请注意，虚拟特征密度用于向布局添加虚拟特征以减少CMP后的拓扑变化。 在操作期间，系统将集成电路的布局离散成多个面板。 接下来，系统计算多个面板的特征密度和松弛密度。 然后，系统通过迭代地计算多个面板的虚拟特征密度，（a）使用特征密度计算多个面板的有效特征密度，以及对CMP过程建模的功能，（b）计算填充量 对于使用目标特征密度，有效特征密度和松弛密度的多个面板中的一组面板，以及（c）更新该组面板的特征密度，松弛密度和虚拟特征密度，使用 填充量。 在本发明的一个实施例中，迭代过程由方差最小化启发式引导，以有效地选择面板集合并且将虚空密度分配/去除到该组面板以减小有效特征密度变化。