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    N-channel and P-channel finFET cell architecture with inter-block insulator
    1.
    发明授权
    N-channel and P-channel finFET cell architecture with inter-block insulator 有权
    N沟道和P沟道finFET单元架构与块间绝缘体

    公开(公告)号：US08561003B2

    公开(公告)日：2013-10-15

    申请号：US13194835

    申请日：2011-07-29

    申请人： Jamil Kawa ,  Victor Moroz ,  Deepak Sherlekar

    发明人： Jamil Kawa ,  Victor Moroz ,  Deepak Sherlekar

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5077 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A finFET block architecture includes a first set of semiconductor fins having a first conductivity type, and a second set of semiconductor fins having a second conductivity type. An inter-block insulator is placed between outer fins of the first and second sets. A patterned gate conductor layer includes a first plurality of gate traces extending across the set of fins in the first block without crossing the inter-block insulator, and a second plurality of gate traces extending across the set of fins in the second block without crossing the inter-block insulator. Patterned conductor layers over the gate conductor layer are arranged in orthogonal layout patterns, and include an inter-block connector arranged to connect gate traces in the first and second blocks.

    摘要翻译： finFET块结构包括具有第一导电类型的第一组半导体鳍片和具有第二导电类型的第二组半导体鳍片。 在第一和第二组的外部散热片之间放置一个块间绝缘体。 图案化栅极导体层包括跨越第一块中的翅片集合延伸的第一多个栅极迹线，而不跨越块间绝缘体;以及第二多个栅极迹线，跨越第二块中的翅片组延伸，而不会穿过第 块间​​绝缘体。 栅极导体层上的图案化导体层以正交布局图案布置，并且包括布置成连接第一和第二块中的栅极迹线的块间连接器。

    N-channel and p-channel finFET cell architecture
    2.
    发明授权
    N-channel and p-channel finFET cell architecture 有权
    N沟道和p沟道finFET单元架构

    公开(公告)号：US08595661B2

    公开(公告)日：2013-11-26

    申请号：US13194862

    申请日：2011-07-29

    申请人： Jamil Kawa ,  Victor Moroz ,  Deepak Sherlekar

    发明人： Jamil Kawa ,  Victor Moroz ,  Deepak Sherlekar

    IPC分类号： G06F17/50

    CPC分类号： H01L27/0886 ,  G06F17/5045 ,  G06F17/5068 ,  G06F17/5072 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/41791 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A finFET block architecture suitable for use of a standard cell library, is based on an arrangement including a first set of semiconductor fins in a first region of the substrate having a first conductivity type, and a second set of semiconductor fins in a second region of the substrate, the second region having a second conductivity type. A patterned gate conductor layer including gate traces in the first and second regions, arranged over channel regions of the first and second sets of semiconductor fins is used for transistor gates. Patterned conductor layers over the gate conductor layer are arranged in orthogonal layout patterns, and can include a plurality of floating power buses over the fins in the first and second regions.

    摘要翻译： 适用于标准单元库的finFET块结构基于包括第一组半导体鳍片的布置，该第一组半导体鳍片在具有第一导电类型的基板的第一区域中，第二组半导体鳍片在第二区域中 所述基板，所述第二区域具有第二导电类型。 在第一和第二区域中包括布置在第一和第二组半导体鳍片的沟道区域上的栅极迹线的图案化栅极导体层用于晶体管栅极。 栅极导体层上的图案化导体层以正交布局图案布置，并且可以包括在第一和第二区域中的翅片上方的多个浮动电源总线。

    N-CHANNEL AND P-CHANNEL FINFET CELL ARCHITECTURE
    3.
    发明申请
    N-CHANNEL AND P-CHANNEL FINFET CELL ARCHITECTURE 有权
    N沟道和P沟道FinFET细胞结构

    公开(公告)号：US20130026572A1

    公开(公告)日：2013-01-31

    申请号：US13194862

    申请日：2011-07-29

    申请人： JAMIL KAWA ,  Victor Moroz ,  Deepak Sherlekar

    发明人： JAMIL KAWA ,  Victor Moroz ,  Deepak Sherlekar

    IPC分类号： H01L27/12 ,  G06F17/50 ,  H01L21/82

    CPC分类号： H01L27/0886 ,  G06F17/5045 ,  G06F17/5068 ,  G06F17/5072 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/41791 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A finFET block architecture suitable for use of a standard cell library, is based on an arrangement including a first set of semiconductor fins in a first region of the substrate having a first conductivity type, and a second set of semiconductor fins in a second region of the substrate, the second region having a second conductivity type. A patterned gate conductor layer including gate traces in the first and second regions, arranged over channel regions of the first and second sets of semiconductor fins is used for transistor gates. Patterned conductor layers over the gate conductor layer are arranged in orthogonal layout patterns, and can include a plurality of floating power buses over the fins in the first and second regions.

    摘要翻译： 适用于标准单元库的finFET块结构基于包括第一组半导体鳍片的布置，该第一组半导体鳍片在具有第一导电类型的基板的第一区域中，第二组半导体鳍片在第二区域中 所述基板，所述第二区域具有第二导电类型。 在第一和第二区域中包括布置在第一和第二组半导体鳍片的沟道区域上的栅极迹线的图案化栅极导体层用于晶体管栅极。 栅极导体层上的图案化导体层以正交布局图案布置，并且可以包括在第一和第二区域中的翅片上方的多个浮动电源总线。

    Method and apparatus for floating or applying voltage to a well of an integrated circuit
    7.
    发明申请
    Method and apparatus for floating or applying voltage to a well of an integrated circuit 有权
    用于浮动或向集成电路的阱施加电压的方法和装置

    公开(公告)号：US20130113547A1

    公开(公告)日：2013-05-09

    申请号：US13374335

    申请日：2011-12-22

    申请人： Victor Moroz ,  Jamil Kawa ,  James D. Sproch ,  Robert B. Lefferts

    发明人： Victor Moroz ,  Jamil Kawa ,  James D. Sproch ,  Robert B. Lefferts

    IPC分类号： G05F1/10

    CPC分类号： H01L27/0207 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0928

    摘要： In one well bias arrangement, no well bias voltage is applied to the n-well, and no well bias voltage is applied to the p-well. Because no external well bias voltage is applied, the n-well and the p-well are floating, even during operation of the devices in the n-well and the p-well. In another well bias arrangement, the lowest available voltage is not applied to the p-well, such as a ground voltage, or the voltage applied to the n+-doped source region of the n-type transistor in the p-well. This occurs even during operation of the n-type transistor in the p-well. In yet another well bias arrangement, the highest available voltage is not applied to the n-well, such as a supply voltage, or the voltage applied to the p+-doped source region of the p-type transistor in the n-well. This occurs even during operation of the p-type transistor in the n-well.

    摘要翻译： 在一个阱偏压布置中，没有良好的偏置电压施加到n阱，并且没有良好的偏置电压施加到p阱。 由于没有施加外部阱偏置电压，即使在n阱和p阱中的器件的操作期间，n阱和p阱都是浮置的。 在另一井偏压装置中，最低可用电压不施加到p阱，例如接地电压，或施加到p阱中n型晶体管的n +掺杂源极区的电压。 即使在p阱中的n型晶体管的操作期间也发生这种情况。 在另一个阱偏压装置中，最高可用电压不施加到n阱，例如电源电压，或施加到n阱中p型晶体管的p +掺杂源极区的电压。 即使在n阱中的p型晶体管的操作期间也会发生这种情况。

    METHOD AND APPARATUS WITH CHANNEL STOP DOPED DEVICES
    9.
    发明申请
    METHOD AND APPARATUS WITH CHANNEL STOP DOPED DEVICES 有权
    具有通道停止装置的方法和装置

    公开(公告)号：US20140154855A1

    公开(公告)日：2014-06-05

    申请号：US13693906

    申请日：2012-12-04

    申请人： Victor Moroz

    发明人： Victor Moroz

    IPC分类号： H01L29/66 ,  G06F17/50

    CPC分类号： H01L21/823878 ,  G06F17/5068 ,  H01L21/76213 ,  H01L21/823821

    摘要： Methods and apparatuses relate to implanting a surface of a semiconductor substrate with dopants, making undoped semiconductor material directly on the surface implanted with the dopants, and making a transistor with a transistor channel in the undoped semiconductor material, such that the transistor channel of the transistor remains undoped throughout manufacture of the integrated circuit.

    摘要翻译： 方法和装置涉及用掺杂剂注入半导体衬底的表面，将未掺杂的半导体材料直接注入到注入掺杂剂的表面上，以及在未掺杂的半导体材料中制造具有晶体管沟道的晶体管，使得晶体管的晶体管沟道 在整个集成电路的制造过程中保持未掺杂。

    N-channel and P-channel end-to-end finFET cell architecture with relaxed gate pitch
    10.
    发明授权
    N-channel and P-channel end-to-end finFET cell architecture with relaxed gate pitch 有权
    N沟道和P沟道端到端finFET单元架构，具有放宽的栅极间距

    公开(公告)号：US08723268B2

    公开(公告)日：2014-05-13

    申请号：US13495810

    申请日：2012-06-13

    申请人： Victor Moroz ,  Deepak D. Sherlekar

    发明人： Victor Moroz ,  Deepak D. Sherlekar

    IPC分类号： H01L29/76

    CPC分类号： H01L27/0924 ,  G06F17/5068 ,  H01L21/823821 ,  H01L23/528 ,  H01L27/0207 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A finFET block architecture uses end-to-end finFET blocks in which the fin lengths are at least twice the contact pitch, whereby there is enough space for interlayer connectors to be placed on the proximal end and the distal end of a given semiconductor fin, and on the gate element on the given semiconductor fin. A first set of semiconductor fins having a first conductivity type and a second set of semiconductor fins having a second conductivity type can be aligned end-to-end. Interlayer connectors can be aligned over corresponding semiconductor fins which connect to gate elements.

    摘要翻译： finFET块结构使用端到端finFET块，其中鳍长度至少为接触间距的两倍，由此在给定半导体鳍片的近端和远端上存在用于层间连接器的足够空间， 并在给定半导体鳍片上的栅极元件上。 具有第一导电类型的第一组半导体鳍片和具有第二导电类型的第二组半导体鳍片可以端对齐地对准。 层间连接器可以对准连接到栅极元件的相应半导体鳍片上。