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公开(公告)号：US08719607B2
公开(公告)日：2014-05-06
申请号：US13308884
申请日：2011-12-01
CPC分类号： G06F1/3293 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A mechanism for power management of processors using Pstates is provided. In a chiplet of a processor in a data processing system, a request is received to change a Pstate from a current Pstate to a requested Pstate. A determination is made as to whether the requested Pstate is less than or equal to a maximum Pstate. Responsive to the requested Pstate being less than or equal to the maximum Pstate, a frequency associated with the requested Pstate is computed thereby forming a computed frequency. An operating frequency of the chiplet is then adjusted to the computed frequency without involvement from a central power control entity.
摘要翻译： 提供了使用Pstates处理器进行电源管理的机制。 在数据处理系统中的处理器的小灯中，接收到将Pstate从当前Pstate更改为所请求的Pstate的请求。 确定所请求的Pstate是否小于或等于最大Pstate。 响应于所请求的Pstate小于或等于最大Pstate，计算与所请求的Pstate相关联的频率，从而形成计算出的频率。 然后将小灯的工作频率调整到计算出的频率，而不受中央功率控制实体的参与。
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公开(公告)号：US20130145188A1
公开(公告)日：2013-06-06
申请号：US13308884
申请日：2011-12-01
IPC分类号： G06F1/32
CPC分类号： G06F1/3293 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A mechanism for power management of processors using Pstates is provided. In a chiplet of a processor in a data processing system, a request is received to change a Pstate from a current Pstate to a requested Pstate. A determination is made as to whether the requested Pstate is less than or equal to a maximum Pstate. Responsive to the requested Pstate being less than or equal to the maximum Pstate, a frequency associated with the requested Pstate is computed thereby forming a computed frequency. An operating frequency of the chiplet is then adjusted to the computed frequency without involvement from a central power control entity.
摘要翻译： 提供了使用Pstates处理器进行电源管理的机制。 在数据处理系统中的处理器的小灯中，接收到将Pstate从当前Pstate更改为所请求的Pstate的请求。 确定所请求的Pstate是否小于或等于最大Pstate。 响应于所请求的Pstate小于或等于最大Pstate，计算与所请求的Pstate相关联的频率，从而形成计算出的频率。 然后将小灯的工作频率调整到计算出的频率，而不受中央功率控制实体的参与。
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3.发明申请SYSTEM AND METHOD FOR DISTRIBUTING SIGNAL WITH EFFICIENCY OVER MICROPROCESSOR 失效通过微处理器分发信号的效率的系统和方法公开(公告)号：US20100161867A1
公开(公告)日：2010-06-24
申请号：US12343594
申请日：2008-12-24
申请人： Matthias Fertig , Tilman Gloekler , Ralph C. Koester , Alexander Erik Mericas , Thomas Pflueger
发明人： Matthias Fertig , Tilman Gloekler , Ralph C. Koester , Alexander Erik Mericas , Thomas Pflueger
IPC分类号： G06F13/36
CPC分类号： G06F13/4247 , G06F11/3466 , G06F11/348 , G06F11/349 , G06F2201/88
摘要： A system and associated method for distributing signals with efficiency over a microprocessor. A performance monitoring unit (PMU) sends configuration signals to a unit to monitor an event occurring on the unit. The unit is attached to a configuration bus and an event bus that are daisy-chained from PMU to other units in the microprocessor. The configuration bus transmits configuration signals from the PMU to the unit to set the unit to report the event. The unit sends event signals to the PMU through the event bus. The unit is configured upon receiving configuration signals comprising a base address of a bus ramp of the unit. A number of units and a number of events for monitoring is flexibly selected by adjusting a length of bit fields within configuration signals.
摘要翻译： 一种用于通过微处理器分配信号的系统和相关方法。 性能监控单元（PMU）将配置信号发送到单元以监视本机发生的事件。 该单元连接到配置总线和从PMU菊花链到微处理器中的其他单元的事件总线。 配置总线将配置信号从PMU发送到单元以设置单元以报告事件。 该单元通过事件总线向PMU发送事件信号。 该单元被配置为接收到包括该单元的总线斜坡的基地址的配置信号。 通过调整配置信号中的位域的长度，可灵活选择多个单元和多个监控事件。
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4.发明申请Method and an Arrangement for Arbitrating Requests to Grant Access to Shared Resources 审中-公开仲裁请求获得共享资源的方法和安排公开(公告)号：US20080172508A1
公开(公告)日：2008-07-17
申请号：US11972648
申请日：2008-01-11
申请人： Tilman Gloekler , Thuyen Le , Thomas Pflueger , Matthias Woehrlc
发明人： Tilman Gloekler , Thuyen Le , Thomas Pflueger , Matthias Woehrlc
IPC分类号： G06F13/372
CPC分类号： G06F13/372
摘要： The present invention relates to a method for arbitrating requests from masters to grant access to shared resources, wherein each master has an individual weight. The method comprises the steps of assigning time slots to the masters depending on the weights of the masters, mapping the current time slot index (32) to a reordering index (30), receiving a plurality of requests from N masters, reordering the requests into a request vector (14) depending on the reordering index (30), searching for predetermined logical values in the request vector (14), generating a grant vector (18) according to the index of the found logical values in the request vector (14), inversely reordering the grant vector (18) into an output grant vector (22) depending on the reordering index (30), and calculating a new time slot index (32) on the basis of the current time slot index (30) and the grant vector (18). Further the present invention relates to a system for performing the method.
摘要翻译： 本发明涉及一种用于仲裁主人的请求以授权对共享资源的访问的方法，其中每个主人具有单独的权重。 该方法包括以下步骤：根据主机的权重向主机分配时隙，将当前时隙索引（32）映射到重新排序索引（30），从N个主机接收多个请求，将请求重新排序 根据重新排序索引（30）的请求向量（14），在请求向量（14）中搜索预定的逻辑值，根据请求向量（14）中找到的逻辑值的索引生成授权向量（18） ），根据所述重排序索引（30）将所述授权向量（18）逆序排列到输出许可向量（22）中，并且基于当前时隙索引（30）计算新的时隙索引（32），以及 授权向量（18）。 此外，本发明涉及一种用于执行该方法的系统。
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5.发明授权公开(公告)号：US08055809B2
公开(公告)日：2011-11-08
申请号：US12343594
申请日：2008-12-24
申请人： Matthias Fertig , Tilman Gloekler , Ralph C. Koester , Alexander Erik Mericas , Thomas Pflueger , Daniel Becker
发明人： Matthias Fertig , Tilman Gloekler , Ralph C. Koester , Alexander Erik Mericas , Thomas Pflueger , Daniel Becker
IPC分类号： G06F3/00
CPC分类号： G06F13/4247 , G06F11/3466 , G06F11/348 , G06F11/349 , G06F2201/88
摘要： A system and associated method for distributing signals with efficiency over a microprocessor. A performance monitoring unit (PMU) sends configuration signals to a unit to monitor an event occurring on the unit. The unit is attached to a configuration bus and an event bus that are daisy-chained from PMU to other units in the microprocessor. The configuration bus transmits configuration signals from the PMU to the unit to set the unit to report the event. The unit sends event signals to the PMU through the event bus. The unit is configured upon receiving configuration signals comprising a base address of a bus ramp of the unit. A number of units and a number of events for monitoring is flexibly selected by adjusting a length of bit fields within configuration signals.
摘要翻译： 一种用于通过微处理器分配信号的系统和相关方法。 性能监视单元（PMU）将配置信号发送到单元以监视本机发生的事件。 该单元连接到配置总线和从PMU菊花链到微处理器中的其他单元的事件总线。 配置总线将配置信号从PMU发送到单元以设置单元以报告事件。 该单元通过事件总线向PMU发送事件信号。 该单元被配置为接收到包括该单元的总线斜坡的基地址的配置信号。 通过调整配置信号中的位域的长度，可灵活选择多个单元和多个监控事件。
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公开(公告)号：US20080167853A1
公开(公告)日：2008-07-10
申请号：US11621361
申请日：2007-01-09
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G01R31/31704 , G01R31/318357 , G06F11/261
摘要： A general purpose computational resource is provided for performing general purpose operations of a system. A special purpose computational resource is coupled to the general purpose computational resource. The special purpose computational resource is provided for: storing test patterns, a description of integrated circuitry, and a description of hardware for testing the integrated circuitry; and executing software for simulating an operation of the described hardware's testing of the described integrated circuitry in response to the test patterns
摘要翻译： 提供通用计算资源用于执行系统的通用操作。 专用计算资源与通用计算资源相连。 专用计算资源用于：存储测试模式，集成电路的描述以及用于测试集成电路的硬件描述; 以及执行用于模拟所述硬件对所述集成电路的测试的响应于所述测试模式的软件
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公开(公告)号：US07386775B2
公开(公告)日：2008-06-10
申请号：US11206846
申请日：2005-08-18
CPC分类号： G01R31/318583
摘要： Methods, apparatus, and products are disclosed for scan verification for a simulated device under test (‘DUT’), the DUT having scan chains, scan inputs, and scan outputs that include verifying correct data entry from the scan inputs of the DUT into the beginning of the scan chain, verifying correct propagation of scan data in the scan chain between the scan inputs and the scan outputs, verifying correct data output from the end of the scan chain to the scan outputs, and leak testing the scan chain with undetermined states for scan cells in the scan chain.
摘要翻译： 公开了用于待测仿真设备（'DUT'）的扫描验证的方法，装置和产品，DUT具有扫描链，扫描输入和扫描输出，其包括验证从DUT的扫描输入的正确数据输入到 扫描链的开始，验证扫描输入和扫描输出之间的扫描链中的扫描数据的正确传播，验证从扫描链的末端输出到扫描输出的正确数据，并对具有未确定状态的扫描链进行泄漏测试 用于扫描链中的扫描单元。
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8.发明授权公开(公告)号：US07350124B2
公开(公告)日：2008-03-25
申请号：US11252512
申请日：2005-10-18
IPC分类号： G06F11/00
CPC分类号： G06F17/5022 , G01R31/318357
摘要： The present invention provides a method, an apparatus, and a computer program product for applying external clock and data patterns for TTP-LBIST. A simulation model for the logic under test is set up in a simulator. Next, a user sets up an external LBIST block, which comprises pre-verified internal clock and data pattern logic, and connects this block to the logic in the simulation model. The internal clock and data pattern logic provides the input patterns used in OPCG modes of LBIST. This internal clock and data pattern logic is already verified through the design effort. Therefore, the internal pattern generators become the external pattern generators in the simulation model. The external LBIST block applies the external clock and data patterns, and subsequently, the user receives and processes these output patterns to determine if the logic operates correctly.
摘要翻译： 本发明提供一种用于对TTP-LBIST应用外部时钟和数据模式的方法，装置和计算机程序产品。 在仿真器中设置了被测逻辑的仿真模型。 接下来，用户设置外部LBIST块，其包括预先验证的内部时钟和数据模式逻辑，并将该块连接到仿真模型中的逻辑。 内部时钟和数据模式逻辑提供了用于LBIST的OPCG模式的输入模式。 该内部时钟和数据模式逻辑已经通过设计工作进行了验证。 因此，内部模式发生器成为模拟模型中的外部模式发生器。 外部LBIST块应用外部时钟和数据模式，随后用户接收并处理这些输出模式以确定逻辑是否正常工作。
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公开(公告)号：US20070061644A1
公开(公告)日：2007-03-15
申请号：US11206846
申请日：2005-08-18
IPC分类号： G01R31/28
CPC分类号： G01R31/318583
摘要： Methods, apparatus, and products are disclosed for scan verification for a simulated device under test (‘DUT’), the DUT having scan chains, scan inputs, and scan outputs that include verifying correct data entry from the scan inputs of the DUT into the beginning of the scan chain, verifying correct propagation of scan data in the scan chain between the scan inputs and the scan outputs, verifying correct data output from the end of the scan chain to the scan outputs, and leak testing the scan chain with undetermined states for scan cells in the scan chain.
摘要翻译： 公开了用于待测仿真设备（'DUT'）的扫描验证的方法，装置和产品，DUT具有扫描链，扫描输入和扫描输出，其包括验证从DUT的扫描输入的正确数据输入到 扫描链的开始，验证扫描输入和扫描输出之间的扫描链中的扫描数据的正确传播，验证从扫描链的末端输出到扫描输出的正确数据，并对具有未确定状态的扫描链进行泄漏测试 用于扫描链中的扫描单元。
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公开(公告)号：US20060190874A1
公开(公告)日：2006-08-24
申请号：US11065601
申请日：2005-02-24
IPC分类号： G06F17/50
CPC分类号： G01R31/318314 , G06F17/5022 , G06F17/504
摘要： A method, system and computer program product for performing verification is disclosed. A high-level description of a design is created and constrained drivers are synthesized from the high-level description of the design. A testbench is generated from the high-level description of the design and the constrained drivers and a formal equivalence is evaluated on the testbench to perform verification.
摘要翻译： 公开了一种用于执行验证的方法，系统和计算机程序产品。 创建对设计的高级描述，并从设计的高级描述合成约束的驱动程序。 测试台是从设计的高级描述和受限制的驱动程序生成的，并且在测试台上进行正式的等效性来执行验证。
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