公开(公告)号：US08940600B2

公开(公告)日：2015-01-27

申请号：US14294152

申请日：2014-06-03

Applicant: United Microelectronics Corp.

Inventor： Chun-Wei Hsu ,  Po-Cheng Huang ,  Ren-Peng Huang ,  Jie-Ning Yang ,  Chia-Lin Hsu ,  Teng-Chun Tsai ,  Chih-Hsun Lin ,  Chang-Hung Kung ,  Yen-Ming Chen ,  Yu-Ting Li

IPC: H01L27/06

CPC classification number: H01L27/0629

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a transistor region and a resistor region; forming a shallow trench isolation (STI) on the resistor region of the substrate; forming a tank in the STI; and forming a resistor in the tank and on two sides of the top surface of the STI outside the tank.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供具有晶体管区域和电阻器区域的衬底; 在衬底的电阻器区域上形成浅沟槽隔离（STI）; 在STI中形成坦克; 并且在罐内形成电阻器，并在罐外部的STI的顶表面的两侧形成电阻器。

公开(公告)号：US20140273371A1

公开(公告)日：2014-09-18

申请号：US14294152

申请日：2014-06-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Wei Hsu ,  Po-Cheng Huang ,  Ren-Peng Huang ,  Jie-Ning Yang ,  Chia-Lin Hsu ,  Teng-Chun Tsai ,  Chih-Hsun Lin ,  Chang-Hung Kung ,  Yen-Ming Chen ,  Yu-Ting Li

IPC: H01L27/06

CPC classification number: H01L27/0629

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a transistor region and a resistor region; forming a shallow trench isolation (STI) on the resistor region of the substrate; forming a tank in the STI; and forming a resistor in the tank and on two sides of the top surface of the STI outside the tank.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供具有晶体管区域和电阻器区域的衬底; 在衬底的电阻器区域上形成浅沟槽隔离（STI）; 在STI中形成坦克; 并且在罐内形成电阻器，并在罐外部的STI的上表面的两侧形成电阻器。

公开(公告)号：US20250169079A1

公开(公告)日：2025-05-22

申请号：US18404839

申请日：2024-01-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Shou Tsai ,  Chau-Chung Hou ,  Yong-Yi Lin ,  Yang-Ju Lu ,  Yu-Lung Shih ,  Ren-Peng Huang ,  Ching-Yang Chuang

IPC: H10B61/00

Abstract: A method of forming a semiconductor structure. A memory structure is formed on a substrate in the memory array region. A dielectric layer is deposited over the memory array region and peripheral region to cover the memory structure. A reverse etching process is performed to remove part of the dielectric layer from the central area of the memory array region, thereby forming an upwardly protruding wall structure along perimeter of the memory array region. The remaining thickness of the dielectric layer in the central area is equal to the sum of a polishing buffer thickness and a target thickness. A first polishing process is performed to remove the upwardly protruding wall structure from the memory array region. A second polishing process is performed to remove upper portion of the dielectric layer with the polishing buffer thickness from the memory array region.

公开(公告)号：US09748144B1

公开(公告)日：2017-08-29

申请号：US15138228

申请日：2016-04-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Ling Lin ,  Yi-Wen Chen ,  Chen-Ming Huang ,  Ren-Peng Huang ,  Ching-Fu Lin

IPC: H01L21/00 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/3213 ,  H01L29/423 ,  H01L21/321 ,  H01L21/033 ,  H01L29/51 ,  H01L21/28 ,  H01L27/11

CPC classification number: H01L21/823456 ,  H01L21/0332 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/31055 ,  H01L21/32115 ,  H01L21/32139 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/1104 ,  H01L27/1116 ,  H01L28/00 ,  H01L29/42376 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

Abstract: First and second semiconductor structures, a CESL, and an ILD layer are formed on a substrate. The first semiconductor structure includes first dummy gate, first nitride mask, and first oxide mask. The second semiconductor structure includes second dummy gate, second nitride mask, and second oxide mask. A first planarization is performed to remove a portion of the ILD layer, exposing CESL. A portion of the CESL, a portion of the ILD layer, the first and the second oxide masks are removed. A hard mask layer is formed on the first and the second nitride masks, and in a recess of the ILD layer. A second planarization is performed to remove a portion of the hard mask layer, the first and the second nitride masks, exposing first and second dummy gates. A remaining portion of the hard mask layer covers the ILD layer.