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    Method for removing oxide
    2.
    发明授权
    Method for removing oxide 有权
    去除氧化物的方法

    公开(公告)号：US08969209B2

    公开(公告)日：2015-03-03

    申请号：US13966276

    申请日：2013-08-13

    Applicant: United Microelectronics Corp.

    Inventor： Yen-Chu Chen ,  Teng-Chun Tsai ,  Chien-Chung Huang ,  Keng-Jen Liu

    IPC: H01L21/302 ,  C23F1/00 ,  H01L21/3065 ,  H01L21/02

    CPC classification number: H01L21/3065 ,  H01L21/02057 ,  H01L21/02063

    Abstract: A method for removing oxide is described. A substrate is provided, including an exposed portion whereon a native oxide layer has been formed. A removing oxide process is performed to the substrate using nitrogen trifluoride (NF3) and ammonia (NH3) as a reactant gas, wherein the volumetric flow rate of NF3 is greater than that of NH3.

    Abstract translation: 描述了一种去除氧化物的方法。 提供了一种衬底，包括其中形成有自然氧化物层的暴露部分。 使用三氟化氮（NF3）和氨（NH3）作为反应气体对基板进行去除氧化处理，其中NF 3的体积流量大于NH 3的体积流量。

    Method for manufacturing CMOS transistor
    6.
    发明授权
    Method for manufacturing CMOS transistor 有权
    制造CMOS晶体管的方法

    公开(公告)号：US09502305B2

    公开(公告)日：2016-11-22

    申请号：US14060568

    申请日：2013-10-22

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Yi-Wei Chen ,  Teng-Chun Tsai ,  Chien-Chung Huang ,  Jei-Ming Chen ,  Tsai-Fu Hsiao

    IPC: H01L21/8238 ,  H01L21/265 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78

    CPC classification number: H01L21/823814 ,  H01L21/26506 ,  H01L21/823807 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/7843

    Abstract: A CMOS transistor and a method for manufacturing the same are disclosed. A semiconductor substrate having at least a PMOS transistor and an NMOS transistor is provided. The source/drain of the PMOS transistor comprises SiGe epitaxial layer. A carbon implantation process is performed to form a carbon-doped layer in the top portion of the source/drain of the PMOS transistor. A silicide layer is formed on the source/drain. A CESL is formed on the PMOS transistor and the NMOS transistor. The formation of the carbon-doped layer is capable of preventing Ge out-diffusion.

    Abstract translation: 公开了一种CMOS晶体管及其制造方法。 提供了至少具有PMOS晶体管和NMOS晶体管的半导体衬底。 PMOS晶体管的源极/漏极包括SiGe外延层。 执行碳注入工艺以在PMOS晶体管的源极/漏极的顶部部分中形成碳掺杂层。 在源极/漏极上形成硅化物层。 在PMOS晶体管和NMOS晶体管上形成CESL。 碳掺杂层的形成能够防止Ge扩散。

    Non-planar semiconductor structure
    7.
    发明授权
    Non-planar semiconductor structure 有权
    非平面半导体结构

    公开(公告)号：US08779513B2

    公开(公告)日：2014-07-15

    申请号：US13869037

    申请日：2013-04-24

    Applicant: United Microelectronics Corp.

    Inventor： Shih-Hung Tsai ,  Chien-Ting Lin ,  Chin-Cheng Chien ,  Chin-Fu Lin ,  Chih-Chien Liu ,  Teng-Chun Tsai ,  Chun-Yuan Wu

    IPC: H01L27/12 ,  H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/785 ,  H01L29/66795

    Abstract: A non-planar semiconductor structure includes a substrate, at least two fin-shaped structures, at least an isolation structure, and a plurality of epitaxial layers. The fin-shaped structures are located on the substrate. The isolation structure is located between the fin-shaped structures, and the isolation structure has a nitrogen-containing layer. The epitaxial layers respectively cover a part of the fin-shaped structures and are located on the nitrogen-containing layer. A non-planar semiconductor process is also provided for forming the semiconductor structure.

    Abstract translation: 非平面半导体结构包括衬底，至少两个鳍状结构，至少一个隔离结构和多个外延层。 鳍状结构位于基底上。 隔离结构位于鳍状结构之间，隔离结构具有含氮层。 外延层分别覆盖了鳍状结构的一部分并且位于含氮层上。 还提供了用于形成半导体结构的非平面半导体工艺。

    METHOD FOR MANUFACTURING CMOS TRANSISTOR
    8.
    发明申请
    METHOD FOR MANUFACTURING CMOS TRANSISTOR 有权
    制造CMOS晶体管的方法

    公开(公告)号：US20140038374A1

    公开(公告)日：2014-02-06

    申请号：US14060568

    申请日：2013-10-22

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Yi-Wei Chen ,  Teng-Chun Tsai ,  Chien-Chung Huang ,  Jei-Ming Chen ,  Tsai-Fu Hsiao

    IPC: H01L21/8238

    CPC classification number: H01L21/823814 ,  H01L21/26506 ,  H01L21/823807 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/7843

    Abstract: A CMOS transistor and a method for manufacturing the same are disclosed. A semiconductor substrate having at least a PMOS transistor and an NMOS transistor is provided. The source/drain of the PMOS transistor comprises SiGe epitaxial layer. A carbon implantation process is performed to form a carbon-doped layer in the top portion of the source/drain of the PMOS transistor. A silicide layer is formed on the source/drain. A CESL is formed on the PMOS transistor and the NMOS transistor. The formation of the carbon-doped layer is capable of preventing Ge out-diffusion.

    Abstract translation: 公开了一种CMOS晶体管及其制造方法。 提供了至少具有PMOS晶体管和NMOS晶体管的半导体衬底。 PMOS晶体管的源极/漏极包括SiGe外延层。 执行碳注入工艺以在PMOS晶体管的源极/漏极的顶部部分中形成碳掺杂层。 在源极/漏极上形成硅化物层。 在PMOS晶体管和NMOS晶体管上形成CESL。 碳掺杂层的形成能够防止Ge扩散。

    SEMICONDUCTOR DEVICE HAVING STRAINED FIN STRUCTURE AND METHOD OF MAKING THE SAME
    10.
    发明申请
    SEMICONDUCTOR DEVICE HAVING STRAINED FIN STRUCTURE AND METHOD OF MAKING THE SAME 有权
    具有应变熔体结构的半导体器件及其制造方法

    公开(公告)号：US20150348971A1

    公开(公告)日：2015-12-03

    申请号：US14825165

    申请日：2015-08-12

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Teng-Chun Tsai ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Cheng Chien ,  Chin-Fu Lin

    IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/165

    CPC classification number: H01L21/845 ,  H01L21/823821 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/165

    Abstract: A semiconductor device includes a semiconductor substrate, at least a first fin structure, at least a second fin structure, a first gate, a second gate, a first source/drain region and a second source/drain region. The semiconductor substrate has at least a first active region to dispose the first fin structure and at least a second active region to dispose the second fin structure. The first/second fin structure partially overlapped by the first/second gate has a first/second stress, and the first stress and the second stress are different from each other. The first/second source/drain region is disposed in the first/second fin structure at two sides of the first/second gate.

    Abstract translation: 半导体器件包括半导体衬底，至少第一鳍结构，至少第二鳍结构，第一栅极，第二栅极，第一源极/漏极区域和第二源极/漏极区域。 半导体衬底至少具有第一有源区以配置第一鳍结构和至少第二有源区以配置第二鳍结构。 与第一/第二栅极部分重叠的第一/第二鳍结构具有第一/第二应力，第一应力和第二应力彼此不同。 第一/第二源极/漏极区域设置在第一/第二栅极的两侧的第一/第二鳍结构中。

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