公开(公告)号：US20180358475A1

公开(公告)日：2018-12-13

申请号：US15655847

申请日：2017-07-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： PENGFEI GUO ,  Shao-Hui Wu ,  HAI BIAO YAO ,  Yu-Cheng Tung ,  Yuanli Ding ,  ZHIBIAO ZHOU

IPC: H01L29/786 ,  H01L29/78 ,  H01L29/49 ,  H01L29/417

CPC classification number: H01L29/78696 ,  H01L29/41733 ,  H01L29/4908 ,  H01L29/78391 ,  H01L29/78648 ,  H01L29/7869

Abstract: A semiconductor device includes a substrate, a source region and a drain region, a gate dielectric layer, and a ferroelectric material layer. The ferroelectric material layer overlaps with the source region and overlaps with the drain region. The substrate further comprises a channel layer. A gate electrode is disposed on the substrate. The ferroelectric material layer is disposed between the channel layer and the gate electrode.

公开(公告)号：US20170256652A1

公开(公告)日：2017-09-07

申请号：US15059311

申请日：2016-03-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： ZHIBIAO ZHOU ,  Shao-Hui Wu ,  Chen-Bin Lin ,  Ding-Lung Chen ,  Chi-Fa Ku

IPC: H01L29/786 ,  H01L21/426 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L21/426 ,  H01L27/1225 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78609 ,  H01L29/78648 ,  H01L29/7869

Abstract: An oxide semiconductor device and a method for manufacturing the same are provided in the present invention. The oxide semiconductor device includes a back gate, an oxide semiconductor film, a pair of source and drain electrodes, agate insulating film, a gate electrode on the oxide semiconductor film with the gate insulating film therebetween, an insulating layer covering only over the gate electrode and the pair of source and drain electrodes, and a top blocking film over the insulating layer.

公开(公告)号：US20170125402A1

公开(公告)日：2017-05-04

申请号：US14956398

申请日：2015-12-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： ZHIBIAO ZHOU ,  Chen-Bin Lin ,  Su Xing ,  Chi-Chang Shuai ,  Chung-Yuan Lee

IPC: H01L27/06 ,  H01L29/861 ,  H01L49/02 ,  H01L29/22 ,  H01L29/06 ,  H01L23/535 ,  H01L29/10 ,  H01L29/24

CPC classification number: H01L27/0629 ,  H01L23/535 ,  H01L27/0727 ,  H01L28/00 ,  H01L28/40 ,  H01L29/0603 ,  H01L29/1079 ,  H01L29/22 ,  H01L29/24 ,  H01L29/861

Abstract: The present invention provides a semiconductor device including a semiconductor substrate, a first well, a second well, a gate electrode, an oxide semiconductor structure and a diode. The first well is disposed in the semiconductor substrate and has a first conductive type, and the second well is also disposed in the semiconductor substrate, adjacent to the first well, and has a second conductive type. The gate electrode is disposed on the first well. The oxide semiconductor structure is disposed on the semiconductor substrate and electrically connected to the second well. The diode is disposed between the first well and the second well.

公开(公告)号：US20230400692A1

公开(公告)日：2023-12-14

申请号：US18236381

申请日：2023-08-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： ZHIBIAO ZHOU

IPC: G02B27/01 ,  H01L33/62 ,  H01L25/075

CPC classification number: G02B27/0172 ,  H01L33/62 ,  H01L25/0753 ,  G02B2027/0178

Abstract: A method of manufacturing a layout structure of Micro LED for augmented reality and mixed reality is provided in the present invention, including steps of providing a substrate with multiple display units arranged thereon to form an unit array and includes an edge region and a transparent region surrounded by the edge region, forming pixel driver circuits and a first transparent layer on the edge region, setting multiple Micro LEDs on the first transparent layer of edge regions, forming a second transparent layer on the Micro LEDs and the first transparent layer, thinning and removing the substrate on the transparent region to expose the first transparent layer, and forming a protection layer on back sides of the substrate and the exposed first transparent layer.

公开(公告)号：US20190066750A1

公开(公告)日：2019-02-28

申请号：US15691729

申请日：2017-08-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yuanli Ding ,  ZHIBIAO ZHOU

IPC: G11C11/22 ,  H01L29/786 ,  H01L29/49

CPC classification number: G11C11/221 ,  G11C5/146 ,  G11C11/223 ,  G11C11/2297 ,  H01L29/4908 ,  H01L29/78648 ,  H01L29/7869

Abstract: A dual mode memory system is provided in the present invention, which includes a memory cell array with a plurality of oxide-semiconductor field effect transistors, each said oxide-semiconductor field effect transistor has a ferroelectric layer in the bottom gate to modulate the bottom gate bias voltage according to the polarization voltages provided by the dual mode control unit.

公开(公告)号：US20180138316A1

公开(公告)日：2018-05-17

申请号：US15853875

申请日：2017-12-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： ZHIBIAO ZHOU ,  Ding-Lung Chen ,  Chen-Bin Lin ,  SANPO WANG ,  Chung-Yuan Lee ,  Chi-Fa Ku

IPC: H01L29/786 ,  H01L29/792 ,  H01L29/788

CPC classification number: H01L29/78609 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/792

Abstract: A semiconductor device is provided in the present invention, which includes a substrate, an oxide-semiconductor layer, source/drain regions, a first dielectric layer covering on the oxide-semiconductor layer and the source/drain regions, a second gate between the two source/drain regions and partially covering the oxide-semiconductor layer, and a charge storage structure between the first gate electrode and the oxide-semiconductor layer.

公开(公告)号：US20170170256A1

公开(公告)日：2017-06-15

申请号：US14996244

申请日：2016-01-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： ZHIBIAO ZHOU ,  Shao-Hui Wu ,  Chi-Fa Ku ,  Chen-Bin Lin

IPC: H01L49/02

CPC classification number: H01L28/91

Abstract: A method for fabricating capacitor is disclosed. The method includes the steps of: providing a material layer; forming a first conductive layer, a first dielectric layer, and a second conductive layer on the material layer; patterning the first dielectric layer and the second conductive layer to form a patterned first dielectric layer and a middle electrode; forming a second dielectric layer on the first conductive layer and the middle electrode; removing part of the second dielectric layer to form a patterned second dielectric layer; forming a third conductive layer on the first conductive layer and the patterned second dielectric layer, wherein the third conductive layer contacts the first conductive layer directly; and removing part of the third conductive layer to expose part of the patterned second dielectric layer.

公开(公告)号：US20230110502A1

公开(公告)日：2023-04-13

申请号：US18082553

申请日：2022-12-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： ZHIBIAO ZHOU

IPC: G02B27/01 ,  H01L33/62 ,  H01L25/075

Abstract: A layout of Micro LED for augmented reality (AR) and mixed reality (MR) is provided in the present invention, including multiple display cells arranging into a cell array, multiple micro LEDs set on the edge region of each display cell and exposing the transparent region surrounded by the edge region, and pixel driver circuits set on the edge region right under the Micro LEDs.

公开(公告)号：US20190279701A1

公开(公告)日：2019-09-12

申请号：US16424485

申请日：2019-05-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yuanli Ding ,  ZHIBIAO ZHOU

IPC: G11C11/22 ,  H01L29/49 ,  H01L29/786

Abstract: A dual mode memory system is provided in the present invention, which includes a memory cell array with a plurality of oxide-semiconductor field effect transistors, each said oxide-semiconductor field effect transistor has a ferroelectric layer in the bottom gate to modulate the bottom gate bias voltage according to the polarization voltages provided by the dual mode control unit.

公开(公告)号：US20180151571A1

公开(公告)日：2018-05-31

申请号：US15361479

申请日：2016-11-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： ZHIBIAO ZHOU ,  Ding-Lung Chen ,  Xing Hua Zhang ,  Shan Liu ,  RUNSHUN WANG ,  Chien-Fu Chen ,  Wei-Jen Wang ,  Chen-Hsien Hsu

IPC: H01L27/11 ,  H01L27/092 ,  H01L29/06

Abstract: The present invention provides a layout of a semiconductor transistor device including a first and a second active area, a first and a second gate, and a metal line. The first active and the second active area are extended along a first direction. The first gate and the second gate are extended along a second direction and crossed the first active area, to define two transistors. The two transistors are electrically connected with each other through a conductive layer. The metal line is disposed on the conductive layer and is electrically connected the two transistors respectively.