公开(公告)号：US11785769B2

公开(公告)日：2023-10-10

申请号：US17857034

申请日：2022-07-03

Applicant: Winbond Electronics Corp.

Inventor： Hsin-Huang Shen ,  Yu-Shu Cheng ,  Yao-Ting Tsai

IPC: H01L29/66 ,  H10B41/30 ,  H01L29/06 ,  H01L29/423 ,  H01L29/788 ,  H01L21/762 ,  H01L21/28 ,  H01L29/78 ,  H10B41/42 ,  H01L21/3213

CPC classification number: H10B41/30 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/66545 ,  H01L29/66598 ,  H01L29/66825 ,  H01L29/7833 ,  H01L29/7883 ,  H10B41/42 ,  H01L21/3213

Abstract: A manufacturing method of semiconductor device is provided. In the manufacturing method, a tunneling dielectric layer, floating gates on the tunneling dielectric layer, an ONO layer on the floating gates, and control gates on the ONO layer are formed. During the formation of the floating gates and the control gates, reactive-ion etching (R.I.E.) is not used at all, and thus damage to the floating and control gates from high-density plasma is prevented, such as charge trap in the floating gates may be significantly reduced to improve the reliability of data storage.

公开(公告)号：US20240244838A1

公开(公告)日：2024-07-18

申请号：US18617590

申请日：2024-03-26

Applicant: Winbond Electronics Corp.

Inventor： Che-Fu Chuang ,  Yao-Ting Tsai ,  Hsiu-Han Liao

IPC: H10B41/30 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/788

CPC classification number: H10B41/30 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/66825 ,  H01L29/7883

Abstract: Provided are a memory device and a method of manufacturing the same. The memory device includes: a stack structure; a first source/drain region and a second source/drain region located in a substrate beside the stack structure; a first self-aligned contact connected to the first source/drain region; a second self-aligned contact connected to the second source/drain region; a first liner structure located between the first self-aligned contact and a first sidewall of the stack structure; and a second liner structure located between the second self-aligned contact and a second sidewall of the stack structure. The first liner structure and the second liner structure are not connected and do not cover the stack structure.

公开(公告)号：US20220123007A1

公开(公告)日：2022-04-21

申请号：US17567850

申请日：2022-01-03

Applicant: Winbond Electronics Corp.

Inventor： Jian-Ting Chen ,  Yao-Ting Tsai ,  Hsiu-Han Liao

IPC: H01L27/11556 ,  H01L29/788 ,  H01L29/66 ,  H01L21/8234

Abstract: Provided is a manufacturing method of a memory device, including: forming a stacked layer on a substrate; patterning the stacked layer to form a plurality of openings in the stacked layer; forming a spacer on a sidewall of the openings; performing a first etching process by using the spacer as a mask to form a plurality of stack structures, wherein the spacer is embedded in the stack structures, such that a width of an upper portion of the stack structures is less than a width of a lower portion thereof; forming a dielectric layer on the stack structures and the spacer; and respectively forming a plurality of contact plugs on the substrate between the stack structures.

公开(公告)号：US11257833B2

公开(公告)日：2022-02-22

申请号：US16568297

申请日：2019-09-12

Applicant: Winbond Electronics Corp.

Inventor： Jian-Ting Chen ,  Yao-Ting Tsai ,  Hsiu-Han Liao

IPC: H01L29/423 ,  H01L27/11556 ,  H01L29/788 ,  H01L29/66 ,  H01L21/8234

Abstract: Provided is a memory device including a substrate, a plurality of stack structures, a spacer, a dielectric layer, and a plurality of contact plugs. The stack structures are disposed on the substrate. The spacer is embedded in the stack structures, so that a width of an upper portion of the stack structures is less than a width of a lower portion thereof. The dielectric layer conformally covers the stack structures and the spacer. The contact plugs are respectively disposed on the substrate between the stack structures.

公开(公告)号：US20220037345A1

公开(公告)日：2022-02-03

申请号：US17376079

申请日：2021-07-14

Applicant: Winbond Electronics Corp.

Inventor： Yao-Ting Tsai ,  Hsiu-Han Liao ,  Che-Fu Chuang

IPC: H01L27/11531 ,  H01L27/11521 ,  H01L29/788 ,  H01L29/66

Abstract: Disposed are a semiconductor structure, a manufacturing method thereof and a flash memory. The semiconductor structure includes a substrate, first isolation structures, a gate structure and an oxide layer. The first isolation structures define a first active area in a peripheral region of the substrate. The oxide layer is disposed on the substrate in the first active area and covered by the first isolation structures. The oxide layer and the first isolation structures define an opening exposing the substrate. The gate structure is disposed on the substrate in the first active area and includes a gate dielectric layer disposed in the opening and a gate disposed on the gate dielectric layer. The oxide layer is located around the gate dielectric layer. The width of the bottom surface of the gate is less than that of the top surface of the first active area.

公开(公告)号：US20200273871A1

公开(公告)日：2020-08-27

申请号：US16568297

申请日：2019-09-12

Applicant: Winbond Electronics Corp.

Inventor： Jian-Ting Chen ,  Yao-Ting Tsai ,  Hsiu-Han Liao

IPC: H01L27/11556 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/788

Abstract: Provided is a memory device including a substrate, a plurality of stack structures, a spacer, a dielectric layer, and a plurality of contact plugs. The stack structures are disposed on the substrate. The spacer is embedded in the stack structures, so that a width of an upper portion of the stack structures is less than a width of a lower portion thereof. The dielectric layer conformally covers the stack structures and the spacer. The contact plugs are respectively disposed on the substrate between the stack structures.

公开(公告)号：US09972631B2

公开(公告)日：2018-05-15

申请号：US15352594

申请日：2016-11-16

Applicant: Winbond Electronics Corp.

Inventor： Che-Fu Chuang ,  Hsiu-Han Liao ,  Yao-Ting Tsai

IPC: H01L27/115 ,  H01L27/11521 ,  H01L29/788 ,  H01L29/423 ,  H01L29/49 ,  H01L29/417 ,  H01L21/28 ,  H01L29/66 ,  H01L27/1157 ,  H01L27/11524

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/11524 ,  H01L27/1157 ,  H01L29/41758 ,  H01L29/42328 ,  H01L29/4975 ,  H01L29/66825 ,  H01L29/7883

Abstract: Provided is a memory device including a substrate and a gate structure. The gate structure is located on the substrate. The gate structure includes a stack gate and a selection gate aside the stack structure. A topmost surface of the selection gate is lower than a topmost surface of the stack gate.

公开(公告)号：US11302705B2

公开(公告)日：2022-04-12

申请号：US16555736

申请日：2019-08-29

Applicant: Winbond Electronics Corp.

Inventor： Chih-Jung Ni ,  Chuan-Chi Chou ,  Yao-Ting Tsai

IPC: H01L27/11521 ,  H01L27/11526 ,  G11C5/06

Abstract: The present invention includes a semiconductor structure having a substrate, a gate structure, and a first spacer. The gate structure includes a floating gate structure, an inter-gate dielectric layer, and a control gate structure. The floating gate structure is disposed on the substrate. The inter-gate dielectric layer is disposed on the floating gate structure. The control gate structure is deposited on the inter-gate dielectric layer and includes an electrode layer, a contact layer and a cap layer. The electrode layer is disposed on the inter-gate dielectric layer. The contact layer is disposed on the electrode layer. The cap layer is disposed on the contact layer. The first spacer is disposed on sidewalls of the control gate structure and covers the electrode layer, the contact layer, and the cap layer. Furthermore, the bottom surface of the first spacer is disposed between the bottom surface and the top surface of the electrode layer.

公开(公告)号：US11257922B2

公开(公告)日：2022-02-22

申请号：US16374162

申请日：2019-04-03

Applicant: Winbond Electronics Corp.

Inventor： Sih-Han Chen ,  Chien-Ting Chen ,  Yao-Ting Tsai ,  Hsiu-Han Liao

IPC: H01L29/66 ,  H01L29/45 ,  H01L21/285

Abstract: A method for forming a self-aligned contact includes providing a substrate with a plurality of gate structures formed on the substrate. The method also includes forming a spacer liner on the gate structures and the substrate. The method also includes forming a sacrificial layer between the gate structures and on the gate structures. The method also includes forming a plurality of dielectric plugs through the sacrificial layer above the gate structures. The method also includes removing the sacrificial layer to form a plurality of contact openings between the gate structures. The method also includes forming an etch resistant layer conformally covering the sidewall and the bottom of the contact openings. The method also includes forming a plurality of contact plugs in the contact openings.

公开(公告)号：US20200343256A1

公开(公告)日：2020-10-29

申请号：US16391326

申请日：2019-04-23

Applicant: Winbond Electronics Corp.

Inventor： Yao-Ting Tsai ,  Che-Fu Chuang ,  Jung-Ho Chang ,  Hsiu-Han Liao

IPC: H01L27/11531 ,  H01L27/11521 ,  H01L21/28 ,  H01L21/285 ,  H01L21/3105 ,  H01L29/66 ,  H01L29/49 ,  H01L29/45 ,  H01L29/78 ,  H01L29/788

Abstract: Provided is an integrated circuit including a substrate, a plurality of first gate structures, a protective layer, a second gate structure, a source region, and a drain region. The substrate has a cell region and a peripheral region. The plurality of first gate structures are disposed in the cell region. A top surface and a sidewall of the plurality of first gate structures are covered by the protective layer. The second gate structure is disposed in the peripheral region. The source region and the drain region are disposed on the both side of the second gate structure. A manufacturing method of the integrated circuit is also provided.