公开(公告)号：US20160372445A1

公开(公告)日：2016-12-22

申请号：US15164660

申请日：2016-05-25

Applicant: XINTEC INC.

Inventor： Ho-Yin YIU ,  Ying-Nan WEN ,  Chien-Hung LIU ,  Wei-Chung YANG

IPC: H01L25/065 ,  H01L23/498 ,  H01L21/56 ,  H01L23/492 ,  H01L21/48 ,  H01L25/00 ,  H01L23/31

CPC classification number: H01L25/065 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/4875 ,  H01L23/3128 ,  H01L23/492 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/49838 ,  H01L25/0655 ,  H01L25/50 ,  H01L27/14618 ,  H01L2224/16 ,  H01L2225/06517 ,  H01L2225/06586 ,  H01L2924/16235

Abstract: A chip package is provided. The chip package includes a substrate having conductive pads therein and adjacent to a first surface thereof. Chips are attached on a second surface opposite to the first surface of the substrate, and an encapsulation layer covers the chips. First redistribution layers are disposed between the second surface of the substrate and the encapsulation layer, and second redistribution layers are disposed on the encapsulation layer. First conductive structures and second conductive structures are disposed in the encapsulation layer. Each of first and second conductive structures respectively includes at least one bonding ball. The first conductive structures are configured to connect first and second redistribution layers, and the second conductive structures are configured to connect the second redistribution layers and the chip. A method of forming the chip package is also provided.

Abstract translation: 提供芯片封装。 芯片封装包括其中具有导电焊盘并且与其第一表面相邻的衬底。 芯片附着在与基板的第一表面相对的第二表面上，并且封装层覆盖芯片。 第一再分配层设置在衬底的第二表面和封装层之间，第二再分布层设置在封装层上。 第一导电结构和第二导电结构设置在封装层中。 第一和第二导电结构中的每一个分别包括至少一个结合球。 第一导电结构被配置为连接第一和第二再分配层，并且第二导电结构被配置为连接第二再分布层和芯片。 还提供了一种形成芯片封装的方法。

公开(公告)号：US20150325557A1

公开(公告)日：2015-11-12

申请号：US14709216

申请日：2015-05-11

Applicant: XINTEC INC.

Inventor： Ho-Yin YIU ,  Ying-Nan WEN ,  Chien-Hung LIU ,  Wei-Chung YANG

IPC: H01L25/16 ,  H01L23/00 ,  H01L27/146 ,  H01L25/00 ,  H01L21/56 ,  H01L23/522 ,  H01L23/31

CPC classification number: H01L24/19 ,  H01L21/56 ,  H01L23/3114 ,  H01L23/3157 ,  H01L23/5226 ,  H01L24/08 ,  H01L24/17 ,  H01L24/20 ,  H01L24/73 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/16 ,  H01L25/50 ,  H01L27/14618 ,  H01L27/14634 ,  H01L2224/0235 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/13144 ,  H01L2224/1403 ,  H01L2224/141 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48465 ,  H01L2224/73209 ,  H01L2224/73215 ,  H01L2224/73217 ,  H01L2224/73227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06568 ,  H01L2924/141 ,  H01L2924/143 ,  H01L2924/1433 ,  H01L2924/146 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2224/82 ,  H01L2924/00

Abstract: A chip package including a first substrate is provided. The first substrate includes a sensing device. A second substrate is attached onto the first substrate and includes an integrated circuit device. A first conductive structure is electrically connected to the sensing device and the integrated circuit device through a redistribution layer disposed on the first substrate. An insulating layer covers the first substrate, the second substrate and the redistribution layer. The insulating layer has a hole therein and a second conductive structure is disposed under the bottom of the hole. A method for forming the chip package is also provided.

Abstract translation: 提供了包括第一基板的芯片封装。 第一基板包括感测装置。 第二基板附着在第一基板上并且包括集成电路装置。 第一导电结构通过设置在第一基板上的再分配层电连接到感测装置和集成电路装置。 绝缘层覆盖第一基板，第二基板和再分布层。 绝缘层在其中具有孔，并且第二导电结构设置在孔的底部下方。 还提供了一种用于形成芯片封装的方法。

公开(公告)号：US20180337142A1

公开(公告)日：2018-11-22

申请号：US15980577

申请日：2018-05-15

Applicant: XINTEC INC.

Inventor： Chia-Ming CHENG ,  Po-Han LEE ,  Wei-Chung YANG ,  Kuan-Jung WU ,  Shu-Ming CHANG

IPC: H01L23/00 ,  H01L25/16 ,  H01L27/146 ,  H01L21/56 ,  H01L23/31 ,  H01L23/04

CPC classification number: H01L23/562 ,  H01L21/56 ,  H01L21/561 ,  H01L23/04 ,  H01L23/3107 ,  H01L23/3128 ,  H01L24/09 ,  H01L24/17 ,  H01L25/167 ,  H01L27/14643 ,  H01L2224/02373

Abstract: A chip package is provided. A first bonding structure is disposed on a first redistribution layer (RDL). A first chip includes a sensing region and a conductive pad that are adjacent to an active surface. The first chip is bonded onto the first RDL through the first bonding structure. The first bonding structure is disposed between the conductive pad and the first RDL. A molding layer covers the first RDL and surrounds the first chip. A second RDL is disposed on the molding layer and the first chip and is electrically connected to the first RDL. A second chip is stacked on a non-active surface of the first chip and is electrically connected to the first chip through the second RDL, the first RDL, and the first bonding structure. A method of forming the chip package is also provided.

公开(公告)号：US20180175092A1

公开(公告)日：2018-06-21

申请号：US15895575

申请日：2018-02-13

Applicant: XINTEC INC.

Inventor： Ho-Yin YIU ,  Ying-Nan WEN ,  Chien-Hung LIU ,  Wei-Chung YANG

IPC: H01L27/146

CPC classification number: H01L27/14634 ,  H01L24/19 ,  H01L27/14618 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/1469 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244

Abstract: A chip package is provided. The chip package includes a sensing device. The chip package also includes a first conductive structure disposed on the sensing device and electrically connected to the sensing device. The chip package further includes a chip and a second conductive structure disposed on the sensing device. The chip includes an integrated circuit device. The second conductive structure is positioned on the chip and is electrically connected to the integrated circuit device and the first conductive structure. In addition, the chip package includes an insulating layer covering the sensing device and the chip. The insulating layer has a hole. The first conductive structure is positioned under the bottom of the hole. The top surface of the insulating layer is coplanar with the top surface of the second conductive structure. A method for forming the chip package is also provided.

公开(公告)号：US20170018590A1

公开(公告)日：2017-01-19

申请号：US15181291

申请日：2016-06-13

Applicant: XINTEC INC.

Inventor： Ho-Yin YIU ,  Ying-Nan WEN ,  Chien-Hung LIU ,  Wei-Chung YANG

IPC: H01L27/146

CPC classification number: H01L27/14634 ,  H01L24/19 ,  H01L27/14618 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/1469 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244

Abstract: A chip package is provided. The chip package includes a sensing device. The chip package also includes a first conductive structure disposed on the sensing device and electrically connected to the sensing device. The chip package further includes a chip and a second conductive structure disposed on the sensing device. The chip includes an integrated circuit device. The second conductive structure is positioned on the chip and is electrically connected to the integrated circuit device and the first conductive structure. In addition, the chip package includes an insulating layer covering the sensing device and the chip. The insulating layer has a hole. The first conductive structure is positioned under the bottom of the hole. The top surface of the insulating layer is coplanar with the top surface of the second conductive structure. A method for forming the chip package is also provided.

Abstract translation: 提供芯片封装。 芯片封装包括感测装置。 芯片封装还包括设置在感测装置上并电连接到感测装置的第一导电结构。 芯片封装还包括设置在感测装置上的芯片和第二导电结构。 该芯片包括集成电路器件。 第二导电结构位于芯片上并与集成电路器件和第一导电结构电连接。 此外，芯片封装包括覆盖感测装置和芯片的绝缘层。 绝缘层具有孔。 第一导电结构位于孔底部。 绝缘层的顶表面与第二导电结构的顶表面共面。 还提供了一种用于形成芯片封装的方法。