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    CHIP PACKAGE AND FABRICATION METHOD THEREOF
    1.
    发明申请
    CHIP PACKAGE AND FABRICATION METHOD THEREOF 有权
    芯片包装及其制造方法

    公开(公告)号：US20160322305A1

    公开(公告)日：2016-11-03

    申请号：US15139276

    申请日：2016-04-26

    Applicant: XINTEC INC.

    Inventor： Shih-Yi LEE ,  Ying-Nan WEN ,  Chien-Hung LIU ,  Ho-Yin YIU

    IPC: H01L23/538 ,  H01L23/544 ,  H01L21/48 ,  H01L21/78

    CPC classification number: H01L23/5389 ,  H01L21/486 ,  H01L21/6835 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/145 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2221/68327 ,  H01L2224/13024 ,  H01L2224/18

    Abstract: A chip package includes a chip, a laser stop layer, a first though hole, an isolation layer, a second though hole and a conductive layer. The laser stop layer is disposed above a first surface of the chip, and the first though hole is extended from a second surface to the first surface of the chip to expose the laser stop layer. The isolation layer is below the second surface and in the first through hole, and the isolation layer has a third surface opposite to the second surface. The second though hole is extended from the third surface to the first surface, and the second though hole is through the first through hole to expose the laser stop layer. The conductive layer is disposed below the third surface and extended into the second though hole to contact the laser stop layer.

    Abstract translation: 芯片封装包括芯片，激光停止层，第一通孔，隔离层，第二通孔和导电层。 激光停止层设置在芯片的第一表面之上，并且第一通孔从芯片的第二表面延伸到第一表面以暴露激光停止层。 隔离层位于第二表面下方，在第一通孔中，隔离层具有与第二表面相对的第三表面。 第二通孔从第三表面延伸到第一表面，第二通孔穿过第一通孔以暴露激光停止层。 导电层设置在第三表面下方并延伸到第二通孔中以接触激光停止层。

    CHIP SCALE SENSING CHIP PACKAGE
    2.
    发明申请
    CHIP SCALE SENSING CHIP PACKAGE 有权

    公开(公告)号：US20170213865A1

    公开(公告)日：2017-07-27

    申请号：US15410715

    申请日：2017-01-19

    Applicant: XINTEC INC.

    Inventor： Ho-Yin YIU ,  Chi-Chang LIAO ,  Shih-Yi LEE ,  Yen-Kang RAW

    IPC: H01L27/146

    CPC classification number: H01L27/14621 ,  H01L27/1462 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/14685 ,  H01L2224/11

    Abstract: This present invention provides a chip scale sensing chip package, comprising: a sensing chip with a first top surface and a first bottom surface opposite to each other, comprising: a sensing device adjacent to the first top surface; and a plurality of conductive pads adjacent to first top surface and the sensing device; a wiring layer formed on the first bottom surface and connected to each of the conductive pads; a dam having a supporter with a first opening and a spacer with a second opening formed on the first top surface, wherein the supporter is within the second opening and adjacent to the spacer, and the spacer is higher than the supporter by a predetermined distance d; a lens formed on the first top surface exposed by the first opening and above the sensing device; and an optical filter deposed on the supporter and above the lens.

    CHIP PACKAGE AND FABRICATION METHOD THEREOF
    3.
    发明申请
    CHIP PACKAGE AND FABRICATION METHOD THEREOF 审中-公开
    芯片包装及其制造方法

    公开(公告)号：US20160229687A1

    公开(公告)日：2016-08-11

    申请号：US15008371

    申请日：2016-01-27

    Applicant: XINTEC INC.

    Inventor： Ying-Nan WEN ,  Ho-Yin YIU ,  Chien-Hung LIU

    IPC: B81B7/00 ,  B81C1/00

    CPC classification number: B81C1/00293 ,  B81B7/02 ,  B81B2201/0235 ,  B81B2201/0242

    Abstract: A chip package included a chip, a first though hole, a laser stop structure, a first isolation layer, a second though hole and a conductive layer. The first though hole is extended from the second surface to the first surface of the chip to expose a conductive pad, and the laser stop structure is disposed on the conductive pad exposed by the first through hole, which an upper surface of the laser stop structure is above the second surface. The first isolation layer covers the second surface and the laser stop structure, and the first isolation layer has a third surface opposite to the second surface. The second though hole is extended from the third surface to the second surface to expose the laser stop structure, and a conductive layer is on the third surface and extended into the second though hole to contact the laser stop structure.

    Abstract translation: 芯片封装包括芯片，第一通孔，激光停止结构，第一隔离层，第二通孔和导电层。 第一通孔从芯片的第二表面延伸到第一表面以暴露导电焊盘，并且激光停止结构设置在由第一通孔暴露的导电焊盘上，激光停止结构的上表面 在第二个表面之上。 第一隔离层覆盖第二表面和激光停止结构，第一隔离层具有与第二表面相对的第三表面。 第二通孔从第三表面延伸到第二表面以暴露激光停止结构，并且导电层在第三表面上并延伸到第二通孔中以接触激光停止结构。

    CHIP PACKAGE AND METHOD FOR FORMING THE SAME
    9.
    发明申请
    CHIP PACKAGE AND METHOD FOR FORMING THE SAME 有权
    芯片包装及其形成方法

    公开(公告)号：US20170018590A1

    公开(公告)日：2017-01-19

    申请号：US15181291

    申请日：2016-06-13

    Applicant: XINTEC INC.

    Inventor： Ho-Yin YIU ,  Ying-Nan WEN ,  Chien-Hung LIU ,  Wei-Chung YANG

    IPC: H01L27/146

    CPC classification number: H01L27/14634 ,  H01L24/19 ,  H01L27/14618 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/1469 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244

    Abstract: A chip package is provided. The chip package includes a sensing device. The chip package also includes a first conductive structure disposed on the sensing device and electrically connected to the sensing device. The chip package further includes a chip and a second conductive structure disposed on the sensing device. The chip includes an integrated circuit device. The second conductive structure is positioned on the chip and is electrically connected to the integrated circuit device and the first conductive structure. In addition, the chip package includes an insulating layer covering the sensing device and the chip. The insulating layer has a hole. The first conductive structure is positioned under the bottom of the hole. The top surface of the insulating layer is coplanar with the top surface of the second conductive structure. A method for forming the chip package is also provided.

    Abstract translation: 提供芯片封装。 芯片封装包括感测装置。 芯片封装还包括设置在感测装置上并电连接到感测装置的第一导电结构。 芯片封装还包括设置在感测装置上的芯片和第二导电结构。 该芯片包括集成电路器件。 第二导电结构位于芯片上并与集成电路器件和第一导电结构电连接。 此外，芯片封装包括覆盖感测装置和芯片的绝缘层。 绝缘层具有孔。 第一导电结构位于孔底部。 绝缘层的顶表面与第二导电结构的顶表面共面。 还提供了一种用于形成芯片封装的方法。

    CHIP PACKAGE AND METHOD FOR FORMING THE SAME
    10.
    发明申请
    CHIP PACKAGE AND METHOD FOR FORMING THE SAME 审中-公开
    芯片包装及其形成方法

    公开(公告)号：US20160233260A1

    公开(公告)日：2016-08-11

    申请号：US15013135

    申请日：2016-02-02

    Applicant: XINTEC INC.

    Inventor： Ho-Yin YIU ,  Ying-Nan WEN ,  Chien-Hung LIU

    IPC: H01L27/146 ,  H01L31/18 ,  H01L31/0232 ,  H01L31/0216

    CPC classification number: H01L27/14636 ,  H01L27/14632 ,  H01L27/14685 ,  H01L27/14687 ,  H01L31/02005 ,  H01L31/0203 ,  H01L31/02327 ,  H01L31/1868 ,  H01L2224/11

    Abstract: An embodiment of the invention provides a chip package which includes a first substrate including a device region and having a first surface and a second surface opposite thereto. A dielectric layer is disposed on the second surface of the first substrate and includes a conducting pad structure connected to the device region, and the first substrate completely covers the conducting pad structure. A second substrate is disposed on the second surface of the first substrate and the dielectric layer is located between the first substrate and the second substrate. The second substrate has a first opening exposing a surface of the conducting pad structure, and a redistribution layer is conformally disposed on a sidewall of the first opening and the surface of the exposed conducting pad structure. A method for forming the chip package is also provided.

    Abstract translation: 本发明的一个实施例提供一种芯片封装，其包括包括器件区域并具有第一表面和与其相对的第二表面的第一衬底。 电介质层设置在第一衬底的第二表面上，并且包括连接到器件区域的导电焊盘结构，并且第一衬底完全覆盖导电焊盘结构。 第二基板设置在第一基板的第二表面上，并且电介质层位于第一基板和第二基板之间。 第二基板具有暴露导电焊盘结构的表面的第一开口，并且再分配层保形地设置在第一开口的侧壁和暴露的导电焊盘结构的表面上。 还提供了一种用于形成芯片封装的方法。

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