公开(公告)号：US20160229687A1

公开(公告)日：2016-08-11

申请号：US15008371

申请日：2016-01-27

Applicant: XINTEC INC.

Inventor： Ying-Nan WEN ,  Ho-Yin YIU ,  Chien-Hung LIU

IPC: B81B7/00 ,  B81C1/00

CPC classification number: B81C1/00293 ,  B81B7/02 ,  B81B2201/0235 ,  B81B2201/0242

Abstract: A chip package included a chip, a first though hole, a laser stop structure, a first isolation layer, a second though hole and a conductive layer. The first though hole is extended from the second surface to the first surface of the chip to expose a conductive pad, and the laser stop structure is disposed on the conductive pad exposed by the first through hole, which an upper surface of the laser stop structure is above the second surface. The first isolation layer covers the second surface and the laser stop structure, and the first isolation layer has a third surface opposite to the second surface. The second though hole is extended from the third surface to the second surface to expose the laser stop structure, and a conductive layer is on the third surface and extended into the second though hole to contact the laser stop structure.

Abstract translation: 芯片封装包括芯片，第一通孔，激光停止结构，第一隔离层，第二通孔和导电层。 第一通孔从芯片的第二表面延伸到第一表面以暴露导电焊盘，并且激光停止结构设置在由第一通孔暴露的导电焊盘上，激光停止结构的上表面 在第二个表面之上。 第一隔离层覆盖第二表面和激光停止结构，第一隔离层具有与第二表面相对的第三表面。 第二通孔从第三表面延伸到第二表面以暴露激光停止结构，并且导电层在第三表面上并延伸到第二通孔中以接触激光停止结构。

公开(公告)号：US20150325551A1

公开(公告)日：2015-11-12

申请号：US14706892

申请日：2015-05-07

Applicant: XINTEC INC.

Inventor： Ying-Nan WEN ,  Chien-Hung LIU

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L24/94 ,  B81B7/007 ,  B81B2207/012 ,  H01L23/3114 ,  H01L23/3128 ,  H01L24/11 ,  H01L24/14 ,  H01L24/19 ,  H01L24/20 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0231 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/1403 ,  H01L2224/14505 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48145 ,  H01L2224/48149 ,  H01L2224/48451 ,  H01L2224/48464 ,  H01L2225/06506 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: A chip package including a first device substrate is provided. The first device substrate is attached to a first surface of a second device substrate. A third device substrate is attached to a second surface of the second device substrate opposite to the first surface. An insulating layer covers the first, second and third device substrates and has at least one opening therein. At least one bump is disposed under a bottom of the opening. A redistribution layer is disposed on the insulating layer and electrically connected to the bump through the opening. A method for forming the chip package is also provided.

公开(公告)号：US20150001710A1

公开(公告)日：2015-01-01

申请号：US14315163

申请日：2014-06-25

Applicant: XINTEC INC.

Inventor： Yi-Ming CHANG ,  Tsang-Yu LIU ,  Yen-Shih HO ,  Ying-Nan WEN

IPC: H01L23/00 ,  H01L23/31

CPC classification number: H01L23/3171 ,  H01L23/3114 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/48 ,  H01L2224/0231 ,  H01L2224/0235 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0361 ,  H01L2224/04042 ,  H01L2224/05007 ,  H01L2224/05026 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05184 ,  H01L2224/05548 ,  H01L2224/05562 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/0558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06155 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/10157 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A chip package is provided. The chip package includes a semiconductor chip, an isolation layer, a redistributing metal layer, and at least a bonding pad. The semiconductor chip includes at least one conducting disposed on a surface of the semiconductor chip. The isolation layer is disposed on the surface of the semiconductor chip, wherein the isolation layer has at least one first opening to expose the first conducting pad. The redistributing metal layer is disposed on the isolation layer and has at least a redistributing metal line corresponding to the conducting pad, the redistributing metal line is connected to the first conducting pad through the first opening. The bonding pad is disposed on the isolation layer and one side of the semiconductor chip, wherein the redistributing metal line extends to the bonding pad to electrically connect the conducting pad to the bonding pad.

Abstract translation: 提供芯片封装。 芯片封装包括半导体芯片，隔离层，再分布金属层和至少一个焊盘。 半导体芯片包括设置在半导体芯片的表面上的至少一个导体。 隔离层设置在半导体芯片的表面上，其中隔离层具有至少一个第一开口以暴露第一导电焊盘。 再分配金属层设置在隔离层上，并且至少具有对应于导电焊盘的再分布金属线，再分布金属线通过第一开口连接到第一导电焊盘。 接合焊盘设置在隔离层和半导体芯片的一侧，其中再分布金属线延伸到接合焊盘，以将导电焊盘电连接到接合焊盘。

公开(公告)号：US20170116458A1

公开(公告)日：2017-04-27

申请号：US15297546

申请日：2016-10-19

Applicant: XINTEC INC.

Inventor： Tsang-Yu LIU ,  Ying-Nan WEN ,  Chi-Chang LIAO ,  Yu-Lung HUANG

IPC: G06K9/00 ,  H01L21/768 ,  H01L23/00 ,  H01L23/08 ,  H01L21/78 ,  H01L23/31 ,  H01L23/04 ,  H01L21/683 ,  H01L21/56

CPC classification number: G06K9/00013 ,  G06K19/0716 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76895 ,  H01L21/78 ,  H01L23/04 ,  H01L23/08 ,  H01L23/15 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3135 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02313 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/03002 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/0579 ,  H01L2224/058 ,  H01L2224/11002 ,  H01L2224/1132 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32058 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2224/92225 ,  H01L2224/94 ,  H01L2924/351 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/014

Abstract: A method for forming a sensing device includes providing a first substrate. The first substrate has a first surface and a second surface opposite thereto. A sensing region is adjacent to the first surface. A temporary cover plate is provided on the second surface to cover the sensing region. The method also includes forming a redistribution layer on the second surface and electrically connected to the sensing region. The method further includes removing the temporary cover plate after the formation of the redistribution layer. The first substrate is bonded to a second substrate and a cover plate after the removal of the temporary cover plate so that the first substrate is positioned between the second substrate and the cover plate. In addition, the method includes filling an encapsulating layer between the second substrate and the cover plate to surround the first substrate.

公开(公告)号：US20160322305A1

公开(公告)日：2016-11-03

申请号：US15139276

申请日：2016-04-26

Applicant: XINTEC INC.

Inventor： Shih-Yi LEE ,  Ying-Nan WEN ,  Chien-Hung LIU ,  Ho-Yin YIU

IPC: H01L23/538 ,  H01L23/544 ,  H01L21/48 ,  H01L21/78

CPC classification number: H01L23/5389 ,  H01L21/486 ,  H01L21/6835 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/145 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2221/68327 ,  H01L2224/13024 ,  H01L2224/18

Abstract: A chip package includes a chip, a laser stop layer, a first though hole, an isolation layer, a second though hole and a conductive layer. The laser stop layer is disposed above a first surface of the chip, and the first though hole is extended from a second surface to the first surface of the chip to expose the laser stop layer. The isolation layer is below the second surface and in the first through hole, and the isolation layer has a third surface opposite to the second surface. The second though hole is extended from the third surface to the first surface, and the second though hole is through the first through hole to expose the laser stop layer. The conductive layer is disposed below the third surface and extended into the second though hole to contact the laser stop layer.

Abstract translation: 芯片封装包括芯片，激光停止层，第一通孔，隔离层，第二通孔和导电层。 激光停止层设置在芯片的第一表面之上，并且第一通孔从芯片的第二表面延伸到第一表面以暴露激光停止层。 隔离层位于第二表面下方，在第一通孔中，隔离层具有与第二表面相对的第三表面。 第二通孔从第三表面延伸到第一表面，第二通孔穿过第一通孔以暴露激光停止层。 导电层设置在第三表面下方并延伸到第二通孔中以接触激光停止层。

公开(公告)号：US20160005787A1

公开(公告)日：2016-01-07

申请号：US14853743

申请日：2015-09-14

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Ying-Nan WEN ,  Tsang-Yu LIU

IPC: H01L27/146

CPC classification number: H01L27/14687 ,  H01L27/14618 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/14685 ,  H01L31/02002 ,  H01L31/0232 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a device region disposed in the semiconductor substrate; a dielectric layer disposed on the first surface of the semiconductor substrate; a conducting pad structure disposed in the dielectric layer and electrically connected to the device region, a carrier substrate disposed on the dielectric layer; and a conducting structure disposed in a bottom surface of the carrier substrate and electrically contacting with the conducting pad structure.

公开(公告)号：US20170047455A1

公开(公告)日：2017-02-16

申请号：US15231590

申请日：2016-08-08

Applicant: XINTEC INC.

Inventor： Ho-Yin YIU ,  Ying-Nan WEN ,  Tsang-Yu LIU

IPC: H01L31/0216 ,  H01L31/18 ,  H01L33/00 ,  H01L33/46 ,  H01L33/52

CPC classification number: H01L33/005 ,  G01S7/4813 ,  G01S17/026 ,  H01L31/173 ,  H01L33/46 ,  H01L33/52 ,  H01L2224/11

Abstract: This present invention provides a novel sensing chip package and a manufacturing method thereof, and in particular provides a proximity sensing chip package and a manufacturing thereof, which is characterized by forming a light blocking layer surrounding the light emitting device of the sensor to block the lateral light emitted by the light emitting device to reduce the interference of the lateral light and enhance the sensitivity of the light sensing device.

Abstract translation: 本发明提供了一种新颖的感测芯片封装及其制造方法，并且特别地提供了一种接近感测芯片封装及其制造方法，其特征在于形成围绕传感器的发光器件的遮光层以阻挡侧面 由发光器件发射的光以减少横向光的干扰并增强光感测装置的灵敏度。

公开(公告)号：US20160372445A1

公开(公告)日：2016-12-22

申请号：US15164660

申请日：2016-05-25

Applicant: XINTEC INC.

Inventor： Ho-Yin YIU ,  Ying-Nan WEN ,  Chien-Hung LIU ,  Wei-Chung YANG

IPC: H01L25/065 ,  H01L23/498 ,  H01L21/56 ,  H01L23/492 ,  H01L21/48 ,  H01L25/00 ,  H01L23/31

CPC classification number: H01L25/065 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/4875 ,  H01L23/3128 ,  H01L23/492 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/49838 ,  H01L25/0655 ,  H01L25/50 ,  H01L27/14618 ,  H01L2224/16 ,  H01L2225/06517 ,  H01L2225/06586 ,  H01L2924/16235

Abstract: A chip package is provided. The chip package includes a substrate having conductive pads therein and adjacent to a first surface thereof. Chips are attached on a second surface opposite to the first surface of the substrate, and an encapsulation layer covers the chips. First redistribution layers are disposed between the second surface of the substrate and the encapsulation layer, and second redistribution layers are disposed on the encapsulation layer. First conductive structures and second conductive structures are disposed in the encapsulation layer. Each of first and second conductive structures respectively includes at least one bonding ball. The first conductive structures are configured to connect first and second redistribution layers, and the second conductive structures are configured to connect the second redistribution layers and the chip. A method of forming the chip package is also provided.

Abstract translation: 提供芯片封装。 芯片封装包括其中具有导电焊盘并且与其第一表面相邻的衬底。 芯片附着在与基板的第一表面相对的第二表面上，并且封装层覆盖芯片。 第一再分配层设置在衬底的第二表面和封装层之间，第二再分布层设置在封装层上。 第一导电结构和第二导电结构设置在封装层中。 第一和第二导电结构中的每一个分别包括至少一个结合球。 第一导电结构被配置为连接第一和第二再分配层，并且第二导电结构被配置为连接第二再分布层和芯片。 还提供了一种形成芯片封装的方法。

公开(公告)号：US20160133588A1

公开(公告)日：2016-05-12

申请号：US14931633

申请日：2015-11-03

Applicant: XINTEC INC.

Inventor： Ho-Yin YIU ,  Ying-Nan WEN ,  Chien-Hung LIU ,  Shih-Yi LEE

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/498 ,  H01L21/311 ,  H01L21/78 ,  H01L21/02 ,  H01L21/683 ,  H01L21/31

CPC classification number: H01L24/09 ,  G06F21/32 ,  H01L21/02013 ,  H01L21/31 ,  H01L21/31111 ,  H01L21/6835 ,  H01L21/76831 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/481 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/17 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02311 ,  H01L2224/02372 ,  H01L2224/02381 ,  H01L2224/03002 ,  H01L2224/03462 ,  H01L2224/0391 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/08235 ,  H01L2224/08237 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2224/03

Abstract: A chip package includes a chip, a laser stopper, an isolation layer, a redistribution layer, an insulating layer, and a conductive structure. The chip has a conductive pad, a first surface, and a second surface. The conductive pad is located on the first surface. The second surface has a first though hole to expose the conductive pad. The laser stopper is located on the conductive pad in the first though hole. The isolation layer is located on the second surface and in the first though hole. The isolation layer has a third surface opposite to the second surface, and has a second though hole to expose the laser stopper. The redistribution layer is located on the third surface, a sidewall of the second though hole, and the laser stopper in the second though hole. The conductive structure is located on the redistribution.

Abstract translation: 芯片封装包括芯片，激光器停止器，隔离层，再分布层，绝缘层和导电结构。 芯片具有导电焊盘，第一表面和第二表面。 导电垫位于第一表面上。 第二表面具有第一通孔以暴露导电垫。 激光停止器位于第一通孔中的导电垫上。 隔离层位于第二表面和第一通孔中。 隔离层具有与第二表面相对的第三表面，并且具有第二通孔以暴露激光制动器。 再分配层位于第三表面，第二通孔的侧壁和第二通孔中的激光停止件。 导电结构位于再分配上。

公开(公告)号：US20150325557A1

公开(公告)日：2015-11-12

申请号：US14709216

申请日：2015-05-11

Applicant: XINTEC INC.

Inventor： Ho-Yin YIU ,  Ying-Nan WEN ,  Chien-Hung LIU ,  Wei-Chung YANG

IPC: H01L25/16 ,  H01L23/00 ,  H01L27/146 ,  H01L25/00 ,  H01L21/56 ,  H01L23/522 ,  H01L23/31

CPC classification number: H01L24/19 ,  H01L21/56 ,  H01L23/3114 ,  H01L23/3157 ,  H01L23/5226 ,  H01L24/08 ,  H01L24/17 ,  H01L24/20 ,  H01L24/73 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/16 ,  H01L25/50 ,  H01L27/14618 ,  H01L27/14634 ,  H01L2224/0235 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/13144 ,  H01L2224/1403 ,  H01L2224/141 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48465 ,  H01L2224/73209 ,  H01L2224/73215 ,  H01L2224/73217 ,  H01L2224/73227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06568 ,  H01L2924/141 ,  H01L2924/143 ,  H01L2924/1433 ,  H01L2924/146 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2224/82 ,  H01L2924/00

Abstract: A chip package including a first substrate is provided. The first substrate includes a sensing device. A second substrate is attached onto the first substrate and includes an integrated circuit device. A first conductive structure is electrically connected to the sensing device and the integrated circuit device through a redistribution layer disposed on the first substrate. An insulating layer covers the first substrate, the second substrate and the redistribution layer. The insulating layer has a hole therein and a second conductive structure is disposed under the bottom of the hole. A method for forming the chip package is also provided.

Abstract translation: 提供了包括第一基板的芯片封装。 第一基板包括感测装置。 第二基板附着在第一基板上并且包括集成电路装置。 第一导电结构通过设置在第一基板上的再分配层电连接到感测装置和集成电路装置。 绝缘层覆盖第一基板，第二基板和再分布层。 绝缘层在其中具有孔，并且第二导电结构设置在孔的底部下方。 还提供了一种用于形成芯片封装的方法。