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388 条记录 (耗时 0.026 秒)

    Sense amplifier
    1.
    发明授权
    Sense amplifier 失效
    感应放大器

    公开(公告)号：US4558241A

    公开(公告)日：1985-12-10

    申请号：US626795

    申请日：1984-07-02

    申请人： Yasuo Suzuki ,  Hiroshi Hirao ,  Yasuaki Suzuki

    发明人： Yasuo Suzuki ,  Hiroshi Hirao ,  Yasuaki Suzuki

    IPC分类号： G11C7/06 ,  G11C11/409 ,  G11C11/419 ,  G11C11/56 ,  H03K5/24 ,  G01R19/165 ,  G11C11/06 ,  H03K3/356

    CPC分类号： G11C11/56 ,  G11C11/5692 ,  G11C7/065 ,  G11C7/06

    摘要： A flip-flop type sense amplifier for a semiconductor memory device is disclosed, the sense amplifier comprising a pair of CMOS inverters cross-coupled with each other to form a CMOS flip-flop circuit having a pair of buffer circuits, for receiving the read-out voltage signals from multi-level memory cells and a predetermined reference voltage, respectively, and a pair of switching circuits for inverting a power source voltage across the flip-flop circuit through common sources of the flip-flop circuit, in response to the transition between a stand-by sequence and a latching operating. The common source of the p-channel transistors of the CMOS flip-flop circuit is connected to a negative potential source, and the common source of the n-channel transistors is connected to a positive potential source during a stand-by sequence, and vice versa, during a latching operation. This unique potential supply method enhances operational speed of the sense amplifier. In a multi-level memory device, a plurality of the sense amplifiers are connected in parallel for the discrimination of the read-out signals changing in a range of a few volts.

    摘要翻译： 公开了一种用于半导体存储器件的触发器型读出放大器，该读出放大器包括一对互相交叉耦合的CMOS反相器，以形成具有一对缓冲电路的CMOS触发器电路， 分别来自多电平存储单元的输出电压信号和预定的参考电压;以及一对开关电路，用于响应于转换，通过触发器电路的公共源来反转触发器电路两端的电源电压 在待机序列和锁定操作之间。 CMOS触发器电路的p沟道晶体管的共同源极连接到负电位源，并且n沟道晶体管的公共源在待机序列期间连接到正电位源， 反之亦然，在锁定操作期间。 这种独特的电位供应方法提高了读出放大器的运行速度。 在多电平存储器件中，多个读出放大器并联连接，用于区分在几伏范围内变化的读出信号。

    Read only memory device with memory cells each storing one of three states
    2.
    发明授权
    Read only memory device with memory cells each storing one of three states 失效
    只读存储器设备，每个存储器单元存储三种状态之一

    公开(公告)号：US4809224A

    公开(公告)日：1989-02-28

    申请号：US82696

    申请日：1987-08-07

    申请人： Yasuo Suzuki ,  Yasuaki Suzuki ,  Hiroshi Hirao

    发明人： Yasuo Suzuki ,  Yasuaki Suzuki ,  Hiroshi Hirao

    IPC分类号： G11C16/04 ,  G11C11/56 ,  G11C7/00 ,  G11C11/40

    CPC分类号： G11C11/5692

    摘要： A ROM device includes a plurality of memory cells each storing one of three states, a cell voltage generating circuit for providing a cell voltage corresponding to the state stored in a selected one of the memory cells, and a reference cell for providing a reference voltage which is substantially the same as the cell voltage provided by a memory cell storing an intermediate state of the three states. The ROM also includes a comparator circuit for generating a logical output signal based on the result of a comparison between the cell voltage and the reference voltage.

    摘要翻译： ROM器件包括多个存储单元，每个存储器单元存储三种状态之一;单元电压产生电路，用于提供对应于存储在所选存储单元中的状态的单元电压;以及参考单元，用于提供参考电压， 与由存储三种状态的中间状态的存储单元提供的单元电压基本相同。 该ROM还包括一个比较器电路，用于根据单元电压和参考电压之间的比较结果产生逻辑输出信号。

    Plural-bit-per-cell read-only memory
    3.
    发明授权
    Plural-bit-per-cell read-only memory 失效
    多单位每单元只读存储器

    公开(公告)号：US4653023A

    公开(公告)日：1987-03-24

    申请号：US651364

    申请日：1984-09-17

    申请人： Yasuo Suzuki ,  Hiroshi Hirao ,  Yasuaki Suzuki

    发明人： Yasuo Suzuki ,  Hiroshi Hirao ,  Yasuaki Suzuki

    IPC分类号： G11C11/56 ,  H01L27/112 ,  G11C17/00 ,  H01L27/10

    CPC分类号： G11C11/5642 ,  G11C11/56 ,  G11C11/5692 ,  H01L27/112 ,  G11C2211/5634

    摘要： A plural-bit-per-cell read-only memory constituted by a memory cell array (1), reference cell array (2A, 2B, 2C), and related circuits. In the memory cell array (1), a low resistance ground line (17) crossing the diffusion layer in parallel with the bit lines (15) is arranged for each predetermined length of the diffusion layer, which is used as a common grounding route to the low resistance ground line (17). The reference cell array (2A) includes a plurality of reference cells (211, 212, . . . 21n), and the arrangement of the reference cells (211, 212, . . . 21n) corresponds to the arrangement of the plural-bit memory cells (14) within the predetermined length of the diffusion layer in the memory cells array (1). The transconductance of the reference cells is predetermined in correspondence with the reference voltage values (REF1, REF2, REF3). A column address signal which selects a plural-bit memory cell (14) also selects one of the reference cells (211, 212, . . . 21n) which corresponds to the plural-bit memory cell (14) selected by the column address signal. Thus, in generation of reference voltages (REF1, REF2, REF3), the reference voltage value is corrected taking into consideration the influence of resistance of the diffusion layer according to the location of the plural-bit memory cell (14) selected by the column address signal.

    摘要翻译： 由存储单元阵列（1），参考单元阵列（2A，2B，2C）和相关电路构成的每单元单位只读存储器。 在存储单元阵列（1）中，对于扩散层的每个预定长度布置与平行于位线（15）的扩散层交叉的低电阻接地线（17），其用作公共接地线路 低电阻接地线（17）。 参考单元阵列（2A）包括多个参考单元（211,212 ...，21n），并且参考单元（211,212 ...，21n）的排列对应于多位 在存储单元阵列（1）中的扩散层的预定长度内的存储单元（14）。 参考单元的跨导是与参考电压值（REF1，REF2，REF3）对应地预定的。 选择多位存储单元（14）的列地址信号还选择与由列地址信号选择的多位存储单元（14）相对应的参考单元（211,212 ... ... 21n）中的一个， 。 因此，在参考电压（REF1，REF2，REF3）的产生中，根据由列选择的多位存储单元（14）的位置考虑扩散层的电阻的影响来校正参考电压值 地址信号。

    Buffer circuit for driving a C-MOS inverter
    4.
    发明授权
    Buffer circuit for driving a C-MOS inverter 失效
    用于驱动C-MOS逆变器的缓冲电路

    公开(公告)号：US4518873A

    公开(公告)日：1985-05-21

    申请号：US407953

    申请日：1982-08-13

    申请人： Yasuo Suzuki ,  Hiroshi Hirao ,  Masanori Nagasawa

    发明人： Yasuo Suzuki ,  Hiroshi Hirao ,  Masanori Nagasawa

    IPC分类号： H03K5/04 ,  G05F3/24 ,  G11C11/409 ,  H03K5/02 ,  H03K17/16 ,  H03K19/00 ,  H03K19/0185 ,  H03K19/0948 ,  H03K17/284 ,  H03K17/26 ,  H03K17/687

    CPC分类号： H03K19/0948 ,  H03K19/0013

    摘要： A buffer circuit for driving a C-MOS inverter, including a first inverter and a second inverter for driving a p-MOS transistor, respectively, and an n-MOS transistor in the C-MOS inverter. Each of the inverters includes at least three transistors connected in series. At least one of the three transistors in each inverter is driven by a delay circuit so that during a transition period of the C-MOS inverter, simultaneous conduction of current through the C-MOS inverter is prevented.

    摘要翻译： 一种用于驱动C-MOS反相器的缓冲电路，包括分别用于驱动p-MOS晶体管的第一反相器和第二反相器，以及C-MOS反相器中的n-MOS晶体管。 每个反相器包括串联连接的至少三个晶体管。 每个逆变器中的三个晶体管中的至少一个由延迟电路驱动，使得在C-MOS反相器的过渡期间，防止同时导通通过C-MOS反相器的电流。

    Read-only memory device
    5.
    发明授权
    Read-only memory device 失效
    只读存储器件

    公开(公告)号：US4489399A

    公开(公告)日：1984-12-18

    申请号：US354500

    申请日：1982-03-03

    申请人： Yasuo Suzuki ,  Hiroshi Hirao

    发明人： Yasuo Suzuki ,  Hiroshi Hirao

    IPC分类号： G11C17/00 ,  G11C11/417 ,  G11C11/419 ,  G11C16/08 ,  G11C16/24 ,  G11C17/12 ,  G11C17/18 ,  G11C7/00

    CPC分类号： G11C17/12 ,  G11C16/08 ,  G11C16/24 ,  G11C17/18

    摘要： A read-only memory device comprises a plurality of groups of bit lines (BL.sub.0, BL.sub.1, . . . , BL.sub.63). One bit line within each group is selected by first column address decoders (4-1) and one group is selected by second column address decoders (8-0.about.8-3). One load element (Q.sub.L0, Q.sub.L1, Q.sub.L2, Q.sub.L3) is provided in each second column address decoder to pull up the potentials of the bit lines.

    摘要翻译： 只读存储器件包括多组位线（BL0，BL1，...，BL63）。 每组中的一个位线由第一列地址解码器（4-1）选择，一组由第二列地址解码器（8-0差分8-3）选择。 在每个第二列地址解码器中提供一个负载元件（QL0，QL1，QL2，QL3）以提升位线的电位。

    Read only memory device having memory cells each storing one of three states
    6.
    发明授权
    Read only memory device having memory cells each storing one of three states 失效
    具有存储单元的只读存储器件，每个存储器单元存储三种状态之一

    公开(公告)号：US4809227A

    公开(公告)日：1989-02-28

    申请号：US82479

    申请日：1987-08-05

    申请人： Yasuo Suzuki ,  Yasuaki Suzuki ,  Nobuo Ikuta

    发明人： Yasuo Suzuki ,  Yasuaki Suzuki ,  Nobuo Ikuta

    IPC分类号： G11C16/04 ,  G11C11/56 ,  H03M7/00 ,  G11C11/40

    CPC分类号： G11C11/56 ,  G11C11/5692 ,  G11C7/1006

    摘要： A read only memory device including: a memory cell array having a plurality of memory cells each storing one of three states; selection means, connected to the memory cell array, for selecting a pair of the memory cells from the memory cell array simultaneously in accordance with an address signal; a first sense amplifier, operatively connected to one of the pair of the memory cells, for producing a three bit output corresponding to the state stored in the one of the pair of the memory cells selected by the selection means; and a second sense amplifier, operatively connected another of the pair of memory cells, for producing a three bit output corresponding to the state stored in the another of the pair of the memory cells selected by the selection means.The device further includes decoder means, connected to the first and second sense amplifiers, for receiving the three bit outputs of the first and second amplifiers and producing a binary three bit output corresponding to the states stored in the pair of memory cells.

    摘要翻译： 一种只读存储器件，包括：存储单元阵列，具有多个存储单元，每个存储单元存储三种状态之一; 选择装置，连接到存储单元阵列，用于根据地址信号同时从存储单元阵列中选择一对存储单元; 第一读出放大器，可操作地连接到所述一对存储器单元中的一个，用于产生与存储在由所述选择装置选择的所述一对存储单元中的一个存储器中的状态相对应的三位输出; 以及第二读出放大器，可操作地连接该对存储器单元中的另一个，用于产生与存储在由选择装置选择的一对存储单元中的另一个中的状态相对应的三位输出。 该装置还包括连接到第一和第二读出放大器的解码器装置，用于接收第一和第二放大器的三位输出，并产生对应于存储在该对存储单元中的状态的二进制三位输出。