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    Cascode circuit employing a depletion-mode, GaN-based FET
    1.
    发明授权
    Cascode circuit employing a depletion-mode, GaN-based FET 有权
    采用耗尽型GaN基FET的串联电路

    公开(公告)号：US07501670B2

    公开(公告)日：2009-03-10

    申请号：US11725760

    申请日：2007-03-20

    申请人： Michael Murphy

    发明人： Michael Murphy

    IPC分类号： H01L31/0328

    CPC分类号： H03K19/0952 ,  H01L27/0605 ,  H01L27/0883 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7786 ,  H03F1/226 ,  H03K17/567 ,  H03K19/09482

    摘要： A circuit includes an input drain, source and gate nodes. The circuit also includes a group III nitride depletion mode FET having a source, drain and gate, wherein the gate of the depletion mode FET is coupled to a potential that maintains the depletion mode FET in its on-state. In addition, the circuit further includes an enhancement mode FET having a source, drain and gate. The source of the depletion mode FET is serially coupled to the drain of the enhancement mode FET. The drain of the depletion mode FET serves as the input drain node, the source of the enhancement mode FET serves as the input source node and the gate of the enhancement mode FET serves as the input gate node.

    摘要翻译： 电路包括输入漏极，源极和栅极节点。 电路还包括具有源极，漏极和栅极的III族氮化物耗尽型FET，其中耗尽型FET的栅极耦合到将耗尽型FET维持在其导通状态的电位。 此外，电路还包括具有源极，漏极和栅极的增强型FET。 耗尽型FET的源极串联耦合到增强型FET的漏极。 耗尽型FET的漏极用作输入漏极节点，增强型FET的源极用作输入源极节点，而增强型FET的栅极用作输入栅极节点。

    Integrable buffer circuit for voltage level conversion having clamping means
    2.
    发明授权
    Integrable buffer circuit for voltage level conversion having clamping means 失效
    具有钳位装置的用于电压电平转换的可积分缓冲电路

    公开(公告)号：US4801824A

    公开(公告)日：1989-01-31

    申请号：US76255

    申请日：1987-07-21

    申请人： Christine Fellinger ,  Josef Einzinger ,  Ludwid Leipold ,  Jenoe Tihanyi ,  Roland Weber

    发明人： Christine Fellinger ,  Josef Einzinger ,  Ludwid Leipold ,  Jenoe Tihanyi ,  Roland Weber

    IPC分类号： H03K17/687 ,  H03K19/0185 ,  H03K19/0948 ,  H03K17/10 ,  H03K5/04 ,  H03K17/16

    CPC分类号： H03K19/09482 ,  H03K19/018507

    摘要： A signal voltage (E) based upon a supply voltage must be converted to a signal voltage (A) with ground reference so as to enable further processing in a logic circuit. A simple level converter comprises a series connection of a MOSFET (T1) connected to the supply voltage; the MOSFET also comprises a resistor (T2). The source terminal of the MOSFET (T1) is located at the potential of the supply voltage. The voltage to be converted is applied between the gate terminal and the source terminal, and the converted voltage occurs at the resistor (T2). The two voltages are each limited by one Zener diode (D2, D1).

    摘要翻译： 基于电源电压的信号电压（E）必须被转换为具有接地参考的信号电压（A），以便能够在逻辑电路中进一步处理。 简单的电平转换器包括连接到电源电压的MOSFET（T1）的串联连接; MOSFET还包括电阻器（T2）。 MOSFET（T1）的源极端子位于电源电压的电位。 要转换的电压施加在栅极端子和源极端子之间，转换的电压发生在电阻器（T2）处。 两个电压都由一个齐纳二极管（D2，D1）限制。

    High speed process-controlled transresistance amplifier
    4.
    发明授权
    High speed process-controlled transresistance amplifier 有权
    高速过程控制跨阻放大器

    公开(公告)号：US06097253A

    公开(公告)日：2000-08-01

    申请号：US248903

    申请日：1999-02-12

    申请人： Jurgen Hissen

    发明人： Jurgen Hissen

    IPC分类号： H03F3/30 ,  H03K19/00 ,  H03K19/017 ,  H03K19/0948 ,  H03F3/16

    CPC分类号： H03K19/01707 ,  H03F3/3028 ,  H03K19/0013 ,  H03K19/09482 ,  H03F2203/45528

    摘要： A high speed, low-power transresistance amplifier incorporating a threshold-biased, current-mode feedback inverter. Starvation transistors are connected between the inverter's power supply terminals and the supply. Capacitors are connected between the power supply and the nodes at which the starvation transistors are connected to the inverter to bypass the starvation transistors and decrease the AC impedance of the nodes, as seen by the inverter. A resistive network connected between the starvation transistors and a bias voltage supply decreases the effective DC impedance of the nodes.

    摘要翻译： 包含门限偏置电流模式反馈逆变器的高速，低功率跨阻放大器。 饥饿晶体管连接在变频器的电源端子和电源之间。 电容器连接在电源和节点之间，饥饿晶体管连接到逆变器以绕过饥饿晶体管并降低节点的AC阻抗，如逆变器所见。 连接在饥饿晶体管和偏压电源之间的电阻网络降低了节点的有效直流阻抗。

    FET inverter with isolated substrate load
    5.
    发明授权
    FET inverter with isolated substrate load 失效
    FET逆变器具有隔离的基板负载

    公开(公告)号：US4072868A

    公开(公告)日：1978-02-07

    申请号：US723678

    申请日：1976-09-16

    申请人： Francisco H. De La Moneda ,  Harish N. Kotecha

    发明人： Francisco H. De La Moneda ,  Harish N. Kotecha

    IPC分类号： H01L21/822 ,  H01L21/82 ,  H01L21/8238 ,  H01L27/04 ,  H01L27/088 ,  H01L27/092 ,  H01L29/78 ,  H03K17/687 ,  H03K19/094 ,  H03K19/0944 ,  H03K19/0948 ,  H03K19/08 ,  H01L27/08 ,  H03K19/40

    CPC分类号： H01L27/092 ,  H01L21/82 ,  H01L27/0883 ,  H03K19/09482 ,  H01L27/0623

    摘要： An insulated Gate Field Effect Transistor (IGFET) static inverter having an improved load line characteristic is disclosed. The inverter comprises an enhancement mode IGFET active device in a first portion of a semiconductor substrate, having its drain connected to an output node, its source connected to a source potential and its gate connected to an input signal source. The first portion of the substrate is connected to a first substrate potential. A depletion mode IGFET load device is located in a second portion of the semiconductor substrate which is electrically isolated from the first portion. The depletion mode load device has its drain connected to a drain potential and its source, gate and the second portion of the semiconductor substrate all connected to the output node. In this manner, the rise in the source-to-substrate voltage bias during the turn-off transition is eliminated in the depletion mode load device, providing an improved load current characteristic for the inverter. Alternate embodiments are disclosed directed to an all N-channel inverter, an all P-channel inverter, and a complementary inverter consisting of a P-channel load device and an N-channel active device.

    摘要翻译： 公开了具有改进的负载线特性的绝缘栅场效应晶体管（IGFET）静态逆变器。 逆变器包括在半导体衬底的第一部分中的增强型IGFET有源器件，其漏极连接到输出节点，其源极连接到源极电势，并且其栅极连接到输入信号源。 衬底的第一部分连接到第一衬底电位。 耗尽型IGFET负载装置位于与第一部分电隔离的半导体衬底的第二部分中。 耗尽型负载装置的漏极连接到漏极电位，其源极，栅极和半导体衬底的第二部分都连接到输出节点。 以这种方式，在耗尽型负载装置中消除了关断转换期间的源至衬底电压偏压的上升，为逆变器提供了改进的负载电流特性。 公开了针对全N通道反相器，全P沟道反相器和由P沟道负载装置和N沟道有源装置组成的互补反相器的替代实施例。

    Output stage circuit for outputting a driving current varying with a process
    6.
    发明授权
    Output stage circuit for outputting a driving current varying with a process 有权
    用于输出随工艺变化的驱动电流的输出级电路

    公开(公告)号：US08536903B2

    公开(公告)日：2013-09-17

    申请号：US13099380

    申请日：2011-05-03

    申请人： Chun Shiah ,  Hao-Jan Yang ,  Ching-Ying Hsu

    发明人： Chun Shiah ,  Hao-Jan Yang ,  Ching-Ying Hsu

    IPC分类号： H03B19/06

    CPC分类号： H03K19/018521 ,  H03K19/09482

    摘要： An output stage circuit includes a first P-type metal-oxide-semiconductor transistor, a second P-type metal-oxide-semiconductor transistor, an N-type metal-oxide-semiconductor transistor, and a current source. A voltage of a third terminal of the first P-type metal-oxide-semiconductor transistor is a first voltage minus a voltage drop between a first terminal and a second terminal of the first P-type metal-oxide-semiconductor transistor. The N-type metal-oxide-semiconductor transistor is coupled between the third terminal of the first P-type metal-oxide-semiconductor transistor and the current source. A second terminal of the second P-type metal-oxide-semiconductor transistor is coupled to the third terminal of the first P-type metal-oxide-semiconductor transistor. When a second terminal of the N-type metal-oxide-semiconductor transistor receives a kick signal, a driving current flowing through the second P-type metal-oxide-semiconductor transistor is relevant to the voltage of the third terminal of the first P-type metal-oxide-semiconductor transistor.

    摘要翻译： 输出级电路包括第一P型金属氧化物半导体晶体管，第二P型金属氧化物半导体晶体管，N型金属氧化物半导体晶体管和电流源。 第一P型金属氧化物半导体晶体管的第三端子的电压是第一电压减去第一P型金属氧化物半导体晶体管的第一端子和第二端子之间的电压降。 N型金属氧化物半导体晶体管耦合在第一P型金属氧化物半导体晶体管的第三端子与电流源之间。 第二P型金属氧化物半导体晶体管的第二端子耦合到第一P型金属氧化物半导体晶体管的第三端子。 当N型金属氧化物半导体晶体管的第二端子接收到反冲信号时，流过第二P型金属氧化物半导体晶体管的驱动电流与第一P型金属氧化物半导体晶体管的第三端子的电压相关， 型金属氧化物半导体晶体管。

    SEMICONDUCTOR APPARATUS
    7.
    发明申请
    SEMICONDUCTOR APPARATUS 有权

    公开(公告)号：US20130135038A1

    公开(公告)日：2013-05-30

    申请号：US13611298

    申请日：2012-09-12

    申请人： Ki Han KIM ,  Hyun Woo LEE ,  Dae Han KWON ,  Chul Woo KIM ,  Soo Bin LIM

    发明人： Ki Han KIM ,  Hyun Woo LEE ,  Dae Han KWON ,  Chul Woo KIM ,  Soo Bin LIM

    IPC分类号： G05F1/10

    CPC分类号： H03K19/094 ,  H03K19/0013 ,  H03K19/09482

    摘要： A semiconductor apparatus includes a power supply changing unit. The power supply changing unit is configured to receive an enable signal and power supply voltage, generate first voltage or second voltage according to the enable signal, change a voltage level of the second voltage according to a level signal, and supply the first voltage or the second voltage as a driving voltage of an internal circuit, wherein the internal circuit receives a first input signal to output a second input signal.

    摘要翻译： 一种半导体装置，包括电源改变单元。 电源改变单元被配置为接收使能信号和电源电压，根据使能信号产生第一电压或第二电压，根据电平信号改变第二电压的电压电平，并且提供第一电压或 第二电压作为内部电路的驱动电压，其中内部电路接收第一输入信号以输出第二输入信号。

    Cascode circuit employing a depletion-mode, GaN-based fet
    8.
    发明申请
    Cascode circuit employing a depletion-mode, GaN-based fet 有权
    采用耗尽型（GaN）的GaN的串联电路

    公开(公告)号：US20080230784A1

    公开(公告)日：2008-09-25

    申请号：US11725760

    申请日：2007-03-20

    申请人： Michael Murphy

    发明人： Michael Murphy

    IPC分类号： H01L31/0256 ,  H01L29/78

    CPC分类号： H03K19/0952 ,  H01L27/0605 ,  H01L27/0883 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7786 ,  H03F1/226 ,  H03K17/567 ,  H03K19/09482

    摘要： A circuit includes an input drain, source and gate nodes. The circuit also includes a group III nitride depletion mode FET having a source, drain and gate, wherein the gate of the depletion mode FET is coupled to a potential that maintains the depletion mode FET in its on-state. In addition, the circuit further includes an enhancement mode FET having a source, drain and gate. The source of the depletion mode FET is serially coupled to the drain of the enhancement mode FET. The drain of the depletion mode FET serves as the input drain node, the source of the enhancement mode FET serves as the input source node and the gate of the enhancement mode FET serves as the input gate node.

    摘要翻译： 电路包括输入漏极，源极和栅极节点。 电路还包括具有源极，漏极和栅极的III族氮化物耗尽型FET，其中耗尽型FET的栅极耦合到将耗尽型FET维持在其导通状态的电位。 此外，电路还包括具有源极，漏极和栅极的增强型FET。 耗尽型FET的源极串联耦合到增强型FET的漏极。 耗尽型FET的漏极用作输入漏极节点，增强型FET的源极用作输入源极节点，而增强型FET的栅极用作输入栅极节点。

    Complementary depletion switch body stack off-chip driver
    9.
    发明授权
    Complementary depletion switch body stack off-chip driver 失效
    互补耗尽开关体堆栈片外驱动

    公开(公告)号：US06177818B1

    公开(公告)日：2001-01-23

    申请号：US09303508

    申请日：1999-04-30

    申请人： Claude L. Bertin ,  Anthony R. Bonaccio ,  Howard L. Kalter ,  Thomas M. Maffitt ,  Jack A. Mandelman ,  William R. Tonti

    发明人： Claude L. Bertin ,  Anthony R. Bonaccio ,  Howard L. Kalter ,  Thomas M. Maffitt ,  Jack A. Mandelman ,  William R. Tonti

    IPC分类号： H03B2100

    CPC分类号： H03K19/09482 ,  H03K19/00361 ,  H03K19/018521

    摘要： An off-chip driver circuit including an enhancement PFET, a depletion PFET, a depletion NFET and an enhancement NFET connected in series. The large enhancement PFET and large enhancement NFET turn off the OCD in tri-state and to turn off the unused half of the OCD to prevent overlap current when driving a ‘0’ or a ‘1’. A first gate signal is applied to the gate of the enhancement PFET and a second gate signal is applied to the enhancement NFET. A fixed voltage is connected to the gate of the depletion NFET and ground to gate of the depletion PFET. An output signal is obtained from a node between the depletion PFET and depletion NFET devices. In another embodiment, a reflection/overshoot sensor 60 is added. The output of sensor is connected to the body of a depletion PFET and an NFET. The feedback from sensor is such that the threshold voltage of the depletion devices are made more positive if the sensor detects that the output is being over-driven. A more positive threshold voltage will reduce the driver's IDS, but leaves the device in the linear mode.

    摘要翻译： 包括增强型PFET，耗尽型PFET，耗尽型NFET和增强型NFET的片外驱动电路。 大增强型PFET和大增强型NFET在三态关闭OCD并关闭OCD的未使用的一半以防止在驱动“0”或“1”时重叠电流。 第一栅极信号被施加到增强PFET的栅极，并且第二栅极信号被施加到增强NFET。 固定电压连接到耗尽型NFET的栅极，并连接到耗尽PFET的栅极。 从耗尽PFET和耗尽NFET器件之间的节点获得输出信号。 在另一个实施例中，添加了反射/过冲传感器60。 传感器的输出连接到耗尽PFET和NFET的主体。 来自传感器的反馈使得如果传感器检测到输出被过驱动，则耗尽装置的阈值电压变得更为正。 更正的阈值电压将减少驾驶员的IDS，但使设备处于线性模式。

    TTL to CMOS input buffer circuit for minimizing power consumption
    10.
    发明授权
    TTL to CMOS input buffer circuit for minimizing power consumption 失效
    TTL到CMOS输入缓冲电路，以最大限度地降低功耗

    公开(公告)号：US4584491A

    公开(公告)日：1986-04-22

    申请号：US570114

    申请日：1984-01-12

    申请人： Richard W. Ulmer

    发明人： Richard W. Ulmer

    IPC分类号： H03K19/00 ,  H03K19/0948 ,  H03K19/094

    CPC分类号： H03K19/0013 ,  H03K19/09482

    摘要： A buffer circuit comprising a current source transistor, a switching transistor and a current sink transistor coupled in series is provided. Control electrodes of the switching transistor and current sink transistor are directly connected and coupled to an input voltage. The buffer circuit has an accurate switchpoint voltage which is substantially process and temperature independent, and the circuit does not consume power for input voltages having low and high CMOS levels.

    摘要翻译： 提供包括串联耦合的电流源晶体管，开关晶体管和电流吸收晶体管的缓冲电路。 开关晶体管和电流宿晶体管的控制电极直接连接并耦合到输入电压。 缓冲电路具有基本上处理和温度无关的精确的开关点电压，并且该电路不消耗具有低和高CMOS电平的输入电压的功率。