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    MEMORY DEVICE TO PRECHARGE BITLINES PRIOR TO SENSING MEMORY CELLS
    2.
    发明公开
    MEMORY DEVICE TO PRECHARGE BITLINES PRIOR TO SENSING MEMORY CELLS 审中-公开

    公开(公告)号：US20240212744A1

    公开(公告)日：2024-06-27

    申请号：US18537685

    申请日：2023-12-12

    申请人： Micron Technology, Inc.

    发明人： Umberto di Vincenzo ,  Ferdinando Bedeschi

    IPC分类号： G11C11/4094 ,  G11C11/4096 ,  G11C11/4099

    CPC分类号： G11C11/4094 ,  G11C11/4096 ,  G11C11/4099

    摘要： Systems, methods, and apparatus related to memory devices. In one approach, a memory device uses an architecture having a precharge transistor in parallel with a cascode transistor. The precharge transistor (e.g., a p-channel device) performs precharging of a bitline to a fixed constant voltage in preparation for sensing a memory cell. The cascode transistor (e.g., an n-channel device) is used to determine the voltage of the bitline during sensing and discharges a sensing node if the memory cell switches (e.g., snaps). The sensing node is coupled to an input of a detector that determines the logic state of the memory cell.

    NON-VOLATILE MEMORY DEVICE AND CONTROL METHOD
    6.
    发明公开
    NON-VOLATILE MEMORY DEVICE AND CONTROL METHOD 审中-公开

    公开(公告)号：US20240079046A1

    公开(公告)日：2024-03-07

    申请号：US18387204

    申请日：2023-11-06

    申请人： YANGTZE MEMORY TECHNOLOGIES CO., LTD.

    发明人： Jianquan Jia ,  Ying Cui ,  Kaikai You

    IPC分类号： G11C11/408 ,  G11C11/4074 ,  G11C11/4094 ,  G11C11/4099 ,  G11C11/419

    CPC分类号： G11C11/4085 ,  G11C11/4074 ,  G11C11/4094 ,  G11C11/4099 ,  G11C11/419

    摘要： A non-volatile memory device includes a memory string, a select gate line coupled to the memory string, word lines coupled to the memory string and including a selected word line, and a control circuit coupled to the select gate line and the word lines, and configured to apply word line pre-pulse signals to at least two groups of the word lines disposed between the select gate line and the selected word line during a pre-charge period. The at least two groups of the word lines include a first group and a second group disposed between the first group and the select gate line. A voltage level of a second word line pre-pulse signal applied to the second group is greater than a voltage level of a first word line pre-pulse signal applied to the first group. A voltage level of at least one word line pre-pulse signal of the word line pre-pulse signals is greater than 0.

    SRAM INCLUDING REFERENCE VOLTAGE GENERATOR AND READ METHOD THEREOF
    7.
    发明公开
    SRAM INCLUDING REFERENCE VOLTAGE GENERATOR AND READ METHOD THEREOF 审中-公开

    公开(公告)号：US20240071479A1

    公开(公告)日：2024-02-29

    申请号：US18347852

    申请日：2023-07-06

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： KYUWON CHOI ,  CHANHO LEE ,  HYEONGCHEOL KIM

    IPC分类号： G11C11/4099 ,  G11C11/4091 ,  G11C11/4094

    CPC分类号： G11C11/4099 ,  G11C11/4091 ,  G11C11/4094

    摘要： A static random access memory includes a memory cell that stores data, a reference voltage generator that generates a reference voltage, a precharge circuit that is connected with the memory cell through a bit line, is connected with the reference voltage generator through a reference bit line, and pre-charges the bit line and the reference bit line, and a sense amplifier that is connected with the bit line and the reference bit line, compares a voltage of the bit line and a voltage of the reference bit line to generate a comparison result, and determines a value of the data stored in the memory cell based on the comparison result. The reference voltage generator includes first-type transistors.

    State detection circuit for anti-fuse memory cell, and memory
    10.
    发明授权
    State detection circuit for anti-fuse memory cell, and memory 有权

    公开(公告)号：US11854605B2

    公开(公告)日：2023-12-26

    申请号：US17570476

    申请日：2022-01-07

    申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

    发明人： Rumin Ji

    IPC分类号： G11C11/4091 ,  G11C11/4074 ,  G11C11/4094 ,  G11C11/4099 ,  G11C17/14

    CPC分类号： G11C11/4091 ,  G11C11/4074 ,  G11C11/4094 ,  G11C11/4099 ,  G11C17/143

    摘要： A state detection circuit for an anti-fuse memory cell includes: amplifier, having first input terminal connected with first reference voltage, second input terminal connected with first node and output terminal connected with second node; anti-fuse memory cell array, including anti-fuse memory cell sub-arrays, bit lines of sub-arrays are connected with first node, word lines of sub-arrays are connected with controller and each sub-array includes anti-fuse memory cells; first switch element, having first terminal connected with power supply, second terminal connected with first node and control terminal connected with second node; second switch element, having first terminal connected with power supply, second terminal connected with third node and control terminal connected with second node; third switch element, having first terminal connected with third node, grounded second terminal and control terminal connected with controller; and comparator, having first and second input terminals connected with third node and second reference voltage respectively.