REFORMATING A PLURALITY OF SIGNALS TO GENERATE A COMBINED SIGNAL COMPRISING A HIGHER DATA RATE THAN A DATA RATE ASSOCIATED WITH THE PLURALITY OF SIGNALS
    91.
    发明申请
    REFORMATING A PLURALITY OF SIGNALS TO GENERATE A COMBINED SIGNAL COMPRISING A HIGHER DATA RATE THAN A DATA RATE ASSOCIATED WITH THE PLURALITY OF SIGNALS 有权
    重新建立信号多样性,以生成包含与信号多样性相关的数据速率的较高数据速率的组合信号

    公开(公告)号:US20150071311A1

    公开(公告)日:2015-03-12

    申请号:US14021035

    申请日:2013-09-09

    CPC classification number: H04J3/16 H04J3/07

    Abstract: Various aspects provide for aggregating a plurality of signals to generate a combined signal. An aggregation component is configured for reformatting a plurality of first signals and combining the plurality of first signals to generate a combined signal that comprises a higher data rate than a data rate associated with the plurality of first signals. A transmitter component is configured for receiving the combined signal and generating one or more data streams based on the combined signal. In an aspect, the aggregation component is additionally configured for reformatting and/or combining the plurality of first signals and at least one second signal to generate the combined signal. In another aspect, a receiver component is configured for generating a pseudo signal at a data rate of the combined signal. In yet another aspect, a de-aggregation component is configured for recovering the plurality of first signals and/or the at least one second signal from the pseudo signal.

    Abstract translation: 各种方面提供聚合多个信号以产生组合信号。 配置聚合组件用于重新格式化多个第一信号并组合多个第一信号以产生包括比与多个第一信号相关联的数据速率更高的数据速率的组合信号。 发射机组件被配置用于接收组合信号并且基于组合信号产生一个或多个数据流。 在一方面,聚合组件另外被配置用于重新格式化和/或组合多个第一信号和至少一个第二信号以产生组合信号。 在另一方面,接收机组件被配置为以组合信号的数据速率产生伪信号。 在另一方面,解聚合组件被配置用于从伪信号中恢复多个第一信号和/或至少一个第二信号。

    RETRIEVAL HASH INDEX
    92.
    发明申请
    RETRIEVAL HASH INDEX 有权
    RETRIEVAL哈希指数

    公开(公告)号:US20150052286A1

    公开(公告)日:2015-02-19

    申请号:US13967607

    申请日:2013-08-15

    Inventor: Kjeld Svendsen

    Abstract: Systems and methods are provided that facilitate retrieval of a hash index in an electronic device. The system contains an addressing component that generates a hash index as a function of an exclusive-or identity. The addressing component can retrieve the hash index as a function of a tag value. Accordingly, required storage area can be reduced and electronic devices can be more efficient.

    Abstract translation: 提供了便于在电子设备中检索散列索引的系统和方法。 该系统包含一个寻址组件,它根据排他或身份生成散列索引。 寻址组件可以根据标签值检索散列索引。 因此,可以减少所需的存储区域,并且电子设备可以更有效率。

    Method for manufacturing a photodetector having a bandwidth tuned honeycomb cell photodiode structure
    93.
    发明授权
    Method for manufacturing a photodetector having a bandwidth tuned honeycomb cell photodiode structure 有权
    具有带宽调谐蜂窝单元光电二极管结构的光电检测器的制造方法

    公开(公告)号:US08906728B2

    公开(公告)日:2014-12-09

    申请号:US14171339

    申请日:2014-02-03

    Abstract: A photodetector with a bandwidth-tuned cell structure is provided. The photodetector is fabricated from a semiconductor substrate that is heavily doped with a first dopant. A plurality of adjoining cavities is formed in the semiconductor substrate having shared cell walls. A semiconductor well is formed in each cavity, moderately doped with a second dopant opposite in polarity to the first dopant. A layer of oxide is grown overlying the semiconductor wells and an annealing process is performed. Then, metal pillars are formed that extend into each semiconductor well having a central axis aligned with an optical path. A first electrode is connected to the metal pillar of each cell, and a second electrode connected to the semiconductor substrate. The capacitance between the first and second electrodes decreases in response to forming an increased number of semiconductor wells with a reduced diameter, and forming metal pillars with a reduced diameter.

    Abstract translation: 提供具有带宽调谐单元结构的光电检测器。 光电检测器由重掺杂第一掺杂剂的半导体衬底制成。 在具有共享单元壁的半导体衬底中形成多个邻接的空腔。 在每个空腔中形成半导体阱,中等掺杂有与第一掺杂剂极性相反的第二掺杂剂。 生长覆盖在半导体阱上的一层氧化物,并进行退火处理。 然后,形成延伸到具有与光路对准的中心轴的每个半导体阱中的金属柱。 第一电极连接到每个电池的金属柱,以及连接到半导体衬底的第二电极。 响应于形成具有减小的直径的增加数量的半导体阱并且形成直径减小的金属柱,第一和第二电极之间的电容减小。

    INTEGRATED CIRCUIT MEMORY DEVICE WITH READ-DISTURB CONTROL
    94.
    发明申请
    INTEGRATED CIRCUIT MEMORY DEVICE WITH READ-DISTURB CONTROL 有权
    具有读干扰控制的集成电路存储器件

    公开(公告)号:US20140307500A1

    公开(公告)日:2014-10-16

    申请号:US13863208

    申请日:2013-04-15

    CPC classification number: G11C11/419 G11C7/02 G11C8/08 G11C11/418

    Abstract: A device (e.g., an integrated circuit memory device such as a static random access memory device) includes word line drivers. Each of the word line drivers includes a pull-up device that is coupled to a node via a shared line. A precharge device is coupled between a power supply and the node. The precharge device and a pull-up device for a selected word line driver are controlled to allow the power supply to charge the node and then to allow the charge stored in the node to flow into a word line corresponding to the selected word line driver.

    Abstract translation: 装置(例如,诸如静态随机存取存储装置的集成电路存储装置)包括字线驱动器。 每个字线驱动器包括经由共享线耦合到节点的上拉设备。 预充电装置耦合在电源和节点之间。 控制用于所选字线驱动器的预充电装置和上拉装置,以允许电源为节点充电,然后允许存储在节点中的电荷流入对应于所选字线驱动器的字线。

    METHOD AND APPARATUS FOR GAPPING
    95.
    发明申请
    METHOD AND APPARATUS FOR GAPPING 有权
    方法和装置

    公开(公告)号:US20140266339A1

    公开(公告)日:2014-09-18

    申请号:US13846171

    申请日:2013-03-18

    CPC classification number: H03L7/06

    Abstract: Systems and methods for generating gapped signals comprising a Delta Sigma Modulator (DSM) configured to generate gapping control signals used to control gap removal rates of an associated gapping unit. The DSM is configured to generate a gapping control signal based on a value of an overflow resulted from performing adding a first number with a remainder of a stored value modulo a second number. The gap removal rates as well as the gap removal resolutions can be adjusted by selecting appropriate values of the first number, the stored value, and the second number. The gapping resolution can be a portion of a pulse. The first number and the second number may be derived from an intended frequency ratio between a gapped signal and a corresponding input signal. The gapping unit may comprise a gapping circuit or a multi-modulus divider.

    Abstract translation: 用于产生有间隙信号的系统和方法包括配置成产生用于控制相关间隙单元的间隙去除速率的间隙控制信号的ΔΣ调制器(DSM)。 DSM被配置为基于通过执行将具有第二数量的存储值的剩余部分的第一数字相加的溢出的值来生成间隙控制信号。 可以通过选择第一个数字,存储值和第二个数字的适当值来调整间隙去除率以及间隙去除分辨率。 间隙分辨率可以是脉冲的一部分。 第一数字和第二数字可以从有间隙信号和对应的输入信号之间的预期频率比率导出。 间隙单元可以包括间隙电路或多模式分配器。

    Frequency synthesis with gapper
    96.
    发明授权
    Frequency synthesis with gapper 有权
    频率合成与缝隙

    公开(公告)号:US08816730B1

    公开(公告)日:2014-08-26

    申请号:US13846311

    申请日:2013-03-18

    CPC classification number: H03L7/06

    Abstract: Systems and methods for frequency synthesis using a gapper. A frequency synthesizer may comprise a gapper, a first integer divider and a Phase Locked Loop (PLL). When a frequency of an output signal is intended to be greater than a corresponding input signal, a factor can be borrowed by the gapper from the first integer divider to generate a rational divide ratio G that is greater 1 in order for the gapper to be capable of performing the division by G. The PLL is capable of multiplying a gapped signal output from the first integer divider and attenuating jitter from the gapped signal.

    Abstract translation: 使用缝隙器进行频率合成的系统和方法。 频率合成器可以包括间隔器,第一整数除法器和锁相环(PLL)。 当输出信号的频率意图大于相应的输入信号时,由第一整数除法器可以通过间隙借用一个因子,以便产生一个大于1的有理分频比G,以使分频器能够 通过G执行除法。PLL能够将从第一整数分频器输出的有间隙信号相乘并衰减来自有间隙信号的抖动。

    SELF-TEST DESIGN FOR SERIALIZER / DESERIALIZER TESTING
    97.
    发明申请
    SELF-TEST DESIGN FOR SERIALIZER / DESERIALIZER TESTING 有权
    用于SERIALIZER / DESERIALIZER测试的自检设计

    公开(公告)号:US20140115409A1

    公开(公告)日:2014-04-24

    申请号:US13654833

    申请日:2012-10-18

    Inventor: Glen Miller

    CPC classification number: G01R31/3177 G01R31/3171 G01R31/31715

    Abstract: Providing for testing of digital sequencing components of an integrated chip is described herein. By way of example, self-test procedures are provided for unidirectional integrated chips that have different sequence generation (e.g., transmission) and sequence monitoring (e.g., receiving) frequencies. A test logic component(s) can be added to an integrated chip to match the sequence generation frequency to the sequence monitoring frequency. This can facilitate self-testing of unidirectional sequence generating components, by modifying a generated sequence at a first datarate to be receivable at a second datarate, and directing the modified sequence to sequence monitoring components of the integrated chip configured to operate at the second datarate.

    Abstract translation: 本文描述了对集成芯片的数字排序组件的测试。 作为示例,为具有不同序列生成(例如,传输)和序列监视(例如,接收)频率的单向集成芯片提供自检程序。 可以将测试逻辑组件添加到集成芯片以将序列生成频率与序列监视频率相匹配。 这可以通过修改在第二数据位可接收的第一数据位上产生的序列,以及将经修改的序列引导到被配置为在第二数据位上操作的集成芯片的序列监视组件,从而促进单向序列生成组件的自检。

    MANAGING BANKS IN A MEMORY SYSTEM
    98.
    发明申请
    MANAGING BANKS IN A MEMORY SYSTEM 有权
    管理存储系统中的银行

    公开(公告)号:US20140101381A1

    公开(公告)日:2014-04-10

    申请号:US13644935

    申请日:2012-10-04

    Inventor: Kjeld Svendsen

    Abstract: Systems and methods are provided that facilitate memory storage in a multi-bank memory device. The system contains a memory controller and a memory array communicatively coupled to the memory controller. The memory controller sends commands to the memory array and the memory array updates or retrieves data contained therein based upon the command. If the memory controller detects a pattern of memory requests, the memory controller can issue a preemptive activation request to the memory array. Accordingly, memory access overhead is reduced.

    Abstract translation: 提供了便于多存储存储器件中的存储器存储的系统和方法。 该系统包含存储器控制器和通信地耦合到存储器控制器的存储器阵列。 存储器控制器将命令发送到存储器阵列,并且存储器阵列基于该命令更新或检索其中包含的数据。 如果存储器控制器检测到存储器请求的模式,则存储器控制器可以向存储器阵列发出先占激活请求。 因此,存储器访问开销降低。

    SYSTEM AND METHOD FOR PROCESS, VOLTAGE, TEMPERATURE (PVT) STABLE DIFFERENTIAL AMPLIFIER TRANSFER FUNCTION
    100.
    发明申请
    SYSTEM AND METHOD FOR PROCESS, VOLTAGE, TEMPERATURE (PVT) STABLE DIFFERENTIAL AMPLIFIER TRANSFER FUNCTION 有权
    过程,电压,温度(PVT)稳定差分放大器传输函数的系统和方法

    公开(公告)号:US20140010333A1

    公开(公告)日:2014-01-09

    申请号:US14021834

    申请日:2013-09-09

    Inventor: Hanan COHEN

    Abstract: A method is provided for process, voltage, temperature (PVT) stable transfer function calibration in a differential amplifier. The gain resistors of a differential amplifier are initially selected to achieve a flat amplitude transfer function in the first frequency band. After calibration, the degeneration capacitor is connected and tuned until a peaked amplitude transfer function is measured, which is resistant to variations in PVT. As an alternative, the degeneration capacitor is not disconnected during initial calibration. Then, the gain resistors and the degeneration capacitor values are selectively adjusted until the first peaked amplitude transfer function is obtained. The peaked amplitude transfer function remains even more stable to variations in PVT than the flat amplitude calibration method.

    Abstract translation: 提供了差分放大器中的过程,电压,温度(PVT)稳定传递函数校准的方法。 最初选择差分放大器的增益电阻以在第一频带中实现平坦的幅度传递函数。 校准后,连接并调谐退化电容,直到测量出峰值的幅度传递函数,这抵消了PVT的变化。 作为替代方案,在初始校准期间,退化电容器不断开。 然后,选择性地调节增益电阻器和退化电容器值,直到获得第一峰值幅度传递函数。 峰值幅度传递函数对于PVT的变化比平坦幅度校准方法保持更稳定。

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