公开(公告)号：US09753695B2

公开(公告)日：2017-09-05

申请号：US14010946

申请日：2013-08-27

Applicant: Analog Devices Global

Inventor： Mikael M. Mortensen ,  Jeffrey G. Bernstein

IPC: G06F7/38 ,  G06F7/60 ,  G06F7/57 ,  G06F1/035

CPC classification number: G06F7/60 ,  G06F1/035 ,  G06F7/57 ,  G06F2101/08 ,  G06F2101/10

Abstract: A datapath circuit may include a digital multiply and accumulate circuit (MAC) and a digital hardware calculator for parallel computation. The digital hardware calculator and the MAC may be coupled to an input memory element for receipt of input operands. The MAC may include a digital multiplier structure with partial product generators coupled to an adder to multiply a first and second input operands and generate a multiplication result. The digital hardware calculator may include a first look-up table coupled between a calculator input and a calculator output register. The first look-up table may include table entry values mapped to corresponding math function results in accordance with a first predetermined mathematical function. The digital hardware calculator may be configured to calculate, based on the first look-up table, a computationally hard mathematical function such as a logarithm function, an exponential function, a division function and a square root function.

公开(公告)号：US20170207801A1

公开(公告)日：2017-07-20

申请号：US15000515

申请日：2016-01-19

Applicant: Analog Devices Global

Inventor： Ahmed Mohammad Ashry Othman

IPC: H04B1/04 ,  H04B17/345

CPC classification number: H04B1/0475 ,  H03G3/3068 ,  H04B1/109 ,  H04B17/345 ,  H04B2001/0416

Abstract: Modular gain control based on blocker signal detection is disclosed herein. In a multi-stage gain control scheme for a receiver, the input stage gain or the pre-mixing stage gain can be controlled for effective blocker rejection based on detecting a blocker signal at a mixer, and the output stage gain or the post-mixing stage gain can be controlled to restore and maintain an appropriate output level after pre-mixing gain reduction performed for blocker rejection. Accordingly, the RF communication systems herein can include multiple loops for providing AGC. In particular, an RF communication system can include a main loop and a blocker loop used to override the main loop when the blocker signal is detected. In certain configurations, the blocker loop reduces the gain of an RF VGA, while the main loop will increase the gain of an IF VGA to restore the output power.

公开(公告)号：US20170201091A1

公开(公告)日：2017-07-13

申请号：US15012108

申请日：2016-02-01

Applicant: Analog Devices Global

Inventor： Bin Shao ,  Yanfeng Lu ,  Scott D. Biederwolf

IPC: H02J1/00

CPC classification number: H02J7/345 ,  H02J2007/0001

Abstract: Apparatus and techniques described herein can include a load circuit comprising a direct current (DC) input terminal, and a source circuit comprising a direct current (DC) output terminal coupled to the DC input terminal of the load circuit. The source circuit can include a source control circuit configured to provide a current-limited DC output voltage and monitor the current-limited DC output voltage to detect an authentication signal provided at the DC output terminal by the load circuit, the load circuit configured to modulate the voltage at the DC output terminal using a pull-down circuit. The load circuit can be configured to compare the supply voltage at the DC input terminal to a reference voltage and, in response, energize other portions of the load circuit when the input current provided the DC input terminal is sufficient as indicated at least in part by the comparison.

公开(公告)号：US20170194001A1

公开(公告)日：2017-07-06

申请号：US15401943

申请日：2017-01-09

Applicant: Analog Devices Global

Inventor： Mikael Mortensen

IPC: G10L15/28 ,  G10L15/10 ,  G10L15/02

CPC classification number: G10L15/28 ,  G10L15/02 ,  G10L15/063 ,  G10L15/08 ,  G10L15/10 ,  G10L15/22 ,  G10L15/265 ,  H04R3/00 ,  H04R2225/43

Abstract: The present invention relates in one aspect to a microphone circuit assembly for an external application processor such as a programmable Digital Signal Processor. The microphone circuit assembly comprises a microphone preamplifier and analog-to-digital converter generate microphone signal samples at a first predetermined rate. A speech feature extractor is configured for receipt and processing of predetermined blocks of the microphone signal samples to extract speech feature vectors representing speech features of the microphone signal samples. The microphone circuit assembly additionally comprises a speech vocabulary comprising a target word or target phrase of human speech encoded as a set of target feature vectors and a decision circuit is configured to compare the speech feature vectors generated by the speech feature extractor with target feature vectors to detect the target speech word or phrase. A controller is configured to generate a recognition signal on an externally accessible output terminal of the microphone circuit assembly in response to a recognized target word or phrase in the microphone signal samples. Additional aspects of the invention relates to Digital Signal Processing Systems comprising the microphone circuit assembly.

公开(公告)号：US20170179969A1

公开(公告)日：2017-06-22

申请号：US15365867

申请日：2016-11-30

Applicant: ANALOG DEVICES GLOBAL

Inventor： Qingdong Meng ,  Hajime Shibata ,  Richard E. Schreier ,  Martin Steven McCormick ,  Yunzhi Dong ,  Jose Barreiro Silva ,  Jialin Zhao ,  Donald W. Paterson ,  Wenhua W. Yang

IPC: H03M1/08 ,  H03M1/12

CPC classification number: H03M1/08 ,  H03M1/124 ,  H03M3/344 ,  H03M3/414

Abstract: For continuous-time multi-stage noise shaping analog-to-digital converters (CT MASH ADCs), quantization noise cancellation often requires accurate estimation of transfer functions, e.g., a noise transfer function of the front end modulator and a signal transfer function of the back end modulator. To provide quantization noise cancellation, digital quantization noise cancellation filters adaptively tracks transfer function variations due to integrator gain errors, flash-to-DAC timing errors, as well as the inter-stage gain and timing errors. Tracking the transfer functions is performed through the direct cross-correlation between the injected maximum length linear feedback shift registers (LFSR) sequence and modulator outputs and then corrects these non-ideal effects by accurately modeling the transfer functions with programmable finite impulse response (PFIR) filters.

公开(公告)号：US09680423B2

公开(公告)日：2017-06-13

申请号：US13798561

申请日：2013-03-13

Applicant: Analog Devices Global

Inventor： Dong Chen

IPC: H03F1/26 ,  H03F1/32 ,  H03F3/189 ,  H03F3/24 ,  H03M1/06 ,  H03M1/12

CPC classification number: H03F1/3247 ,  H03F1/3258 ,  H03F3/189 ,  H03F3/245 ,  H03F2201/3209 ,  H03F2201/3224 ,  H03F2201/3233 ,  H03M1/0614 ,  H03M1/1245

Abstract: A amplifier system may include a predistorter receiving an input signal to generate a predistortion signal, a first converter receiving the predistortion signal to generate a preamplified signal, a power amplifier receiving the preamplified signal to generate an output signal based on the preamplified signal and the input signal, and a second converter sampling the output signal to generate a feedback signal. The power amplifier may produce a distortion signal at a first frequency, the second converter may sample the output signal using a timing signal with a second frequency that is lower than the first frequency to generate the feedback signal, and the predistorter, based upon the feedback signal, may predistort the predistortion signal to reduce the distortion signal at the first frequency.

公开(公告)号：US20170154715A1

公开(公告)日：2017-06-01

申请号：US14974744

申请日：2015-12-18

Applicant: Analog Devices Global

Inventor： Ke Li

IPC: H01F7/06 ,  G01F1/58 ,  G01F1/60 ,  H01F27/28

CPC classification number: G01F1/60 ,  G01F1/584 ,  G01F1/586 ,  H01F7/064 ,  H01F27/2804 ,  H03F3/04 ,  H03F3/45076 ,  H03F2200/129 ,  H03F2200/261 ,  H03F2203/45116 ,  H03M1/12 ,  H03M1/66

Abstract: An interface circuit to an electromagnetic flow sensor is described. In an example, it can provide a DC coupled signal path from the electromagnetic flow sensor to an analog-to-digital converter (ADC) circuit. Examples with differential and pseudo-differential signal paths are described. Examples providing DC offset or low frequency noise compensation or cancellation are described. High input impedance examples are described. Coil excitation circuits are described, such as can provide on-chip inductive isolation between signal inputs and signal outputs. A switched mode power supply can be used to actively manage a bias voltage of an H-Bridge, such as to boost the current provided by the H-Bridge to the sensor coil during select time periods, such as during phase shift time periods of the coil, which can help reduce or minimize transient noise during such time periods.

公开(公告)号：US09659717B2

公开(公告)日：2017-05-23

申请号：US14182839

申请日：2014-02-18

Applicant: Analog Devices Global

Inventor： Check F. Lee ,  Raymond C. Goggin ,  Padraig L. Fitzgerald

IPC: H01L41/09 ,  B81B7/04 ,  H01H1/00 ,  B81B7/00 ,  B81C1/00 ,  H01H59/00 ,  H01P1/12

CPC classification number: H01H1/0036 ,  B81B7/0064 ,  B81B2201/014 ,  B81B2207/03 ,  B81B2207/07 ,  B81B2207/115 ,  B81C1/00698 ,  B81C2201/0171 ,  B81C2203/075 ,  H01H59/0009 ,  H01P1/127

Abstract: A MEMS apparatus has a substrate, an input node, an output node, and a MEMS switch between the input node and the output node. The switch selectively connects the input node and the output node, which are electrically isolated when the switch is open. The apparatus also has an input doped region in the substrate and an output doped region in the substrate. The input doped region and output doped region are electrically isolated through the substrate—i.e., the resistance between them inhibits non-negligible current flows between the two doped regions. The input doped region forms an input capacitance with the input node, while the output doped region forms an output capacitance with the output node.

公开(公告)号：US20170134019A1

公开(公告)日：2017-05-11

申请号：US14937705

申请日：2015-11-10

Applicant: Analog Devices Global

Inventor： Edward John Coyne

IPC: H03K17/567

CPC classification number: H03K17/567 ,  H01L27/0266 ,  H01L29/735 ,  H03K17/165 ,  H03K17/168

Abstract: A transistor switch device is provided that exhibits relatively good voltage capability and relatively easy drive requirements to turn the device on and off. This can reduce transient drive current flows that may perturb other components.

公开(公告)号：US20170133841A1

公开(公告)日：2017-05-11

申请号：US14937771

申请日：2015-11-10

Applicant: Analog Devices Global

Inventor： Edward John Coyne

IPC: H02H9/04 ,  H01L23/58 ,  H01L29/808 ,  H01L27/02 ,  H01L27/06

CPC classification number: H02H9/046 ,  H01L23/58 ,  H01L27/0248 ,  H01L27/0259 ,  H01L27/0266 ,  H01L27/0623 ,  H01L29/0653 ,  H01L29/0688 ,  H01L29/1066 ,  H01L29/8083

Abstract: Components can be damaged if they are exposed to excess voltages. A device is disclosed herein which can be placed in series with a component and a node that may be exposed to high voltages. If the voltage becomes too high, the device can autonomously switch into a relatively high impedance state, thereby protecting the other components.