公开(公告)号：US10536553B1

公开(公告)日：2020-01-14

申请号：US14846460

申请日：2015-09-04

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Mitchell G. Poplack ,  Sharon Mutchnik ,  Hitesh Gannu ,  Ramesh Mogili

IPC: G06F13/00 ,  H04L29/08

Abstract: An emulation system comprises an outband traffic generating device comprising at least one field programmable gate array coupled to a host system. The outband traffic generating device is configured to transfer one or more bits via an outband channel to a register of an inband traffic generating device. The inband traffic generating device comprises at least one field programmable gate array coupled to a target system. The inband traffic generating device is configured to transfer the one or more bits via an inband channel to the outband traffic generating device.

公开(公告)号：US10521543B1

公开(公告)日：2019-12-31

申请号：US15642848

申请日：2017-07-06

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Laurent Saint-Marcel

IPC: G06F17/50 ,  G06F16/532

Abstract: Disclosed herein are embodiments of systems, methods, and products for dynamically determining and rendering a target resistance of a partially routed net between two circuit devices in an integrated circuit (IC) design and automatically resizing a wire segment being edited in real time based on the target resistance such that the fully routed net satisfies the maximum resistance constraint. Therefore, the embodiments disclosed herein simplify the circuit designer's job and improves design productivity. Unlike conventional systems, an EDA tool disclosed herein does not have to route the full net between two circuit devices to run design rule checking (DRC). Thus, the EDA tool does not require multiple iterations of fully routing a net and checking for DRC violations such that the maximum resistance constraint is not violated.

公开(公告)号：US10521531B1

公开(公告)日：2019-12-31

申请号：US15808326

申请日：2017-11-09

Applicant: Cadence Design Systems, Inc.

Inventor： Frederico Nascimento-Yoshida ,  Matheus Nogueira Fonseca

IPC: G06F9/455 ,  G06F17/50 ,  H04W80/12

Abstract: The present disclosure relates to a method for formal verification of an electronic design. Embodiments may include receiving, using a processor, an electronic design having a plurality of clock configurations associated therewith and identifying a target clock configuration associated with the electronic design. Embodiments may also include receiving a range of clock factor values from a user, wherein each clock factor value corresponds to a frequency of the target clock configuration. Embodiments may further include selecting, via a formal engine, at least one clock factor value from the range and selecting, via the formal engine, at least one clock phase associated with the target clock configuration. Embodiments may also include performing formal verification of the electronic design, based upon, at least in part, the at least one clock factor value or the at least one clock phase.

公开(公告)号：US10515176B1

公开(公告)日：2019-12-24

申请号：US15298178

申请日：2016-10-19

Applicant: Cadence Design Systems, Inc.

Inventor： Uri Joel Maoz ,  Ronen Shoham

IPC: G06F17/50

Abstract: The present disclosure relates to a computer-implemented method for visualizing one or more IP-XACT component data routes is provided. The method may include receiving, using at least one processor, an IP-XACT description of one or design elements including at least one target ingress interface, and at least one of an initiator egress interface, a memory map and an address space. The method may further include analyzing, using the at least one processor, the IP-XACT description of the one or design elements and displaying a graphical user interface, based upon, at least in part, the IP-XACT description of one or design elements, wherein the graphical user interface is configured to display the at least one target ingress interface, and any number of the initiator egress interface, the memory map and the address space.

公开(公告)号：US10509878B1

公开(公告)日：2019-12-17

申请号：US15688730

申请日：2017-08-28

Applicant: Cadence Design Systems, Inc.

Inventor： Yi-Xiao Ding ,  Zhuo Li ,  Wen-Hao Liu

IPC: G06F17/50 ,  G06F1/10

Abstract: Systems, methods, media, and other such embodiments are described for routing track assignment in a circuit design. One embodiment involves accessing routing data for a circuit design, and a first wire of a plurality of wires in the routing data. A second wire is identified that is related to the first wire as a parent wire along a shared routing direction. A misalignment value is calculated for the first wire and the second wire, and a new routing placement is selected for the first wire based at least in part on the misalignment value. In some embodiments, all wires in various routings of a circuit design are checked for possible misalignment in order to improve slew performance via reduction of unnecessary vias.

公开(公告)号：US10476658B1

公开(公告)日：2019-11-12

申请号：US15714756

申请日：2017-09-25

Applicant: Cadence Design Systems, Inc.

Inventor： Sathish Kumar Ganesan ,  Fred Staples Stivers

IPC: H04L7/033

Abstract: Disclosed is an improved approach to implement clock alignments between a test subject and its corresponding controller device. Phase locking is performed for the clocks between the test subject and controller device via a training sequence to obtain the appropriate alignment(s). Alignment logic is included on both the testchip and the controller device to implement alignment.

公开(公告)号：US10460069B1

公开(公告)日：2019-10-29

申请号：US14984844

申请日：2015-12-30

Applicant: Cadence Design Systems, Inc. ,  Robert Bosch GmbH

Inventor： Thomas Burdick ,  Peter Herth ,  Göran Jerke ,  Christel Bürzele ,  Daniel Marolt ,  Vinko Marolt

IPC: G06F17/50

Abstract: Electronic design automation systems and methods for functional reactive parameterized cells (FR-PCells) are described. In one embodiment, a PCell includes a reactive parameter that is based on context information regarding other cells or elements of an overall circuit design. Processing of the FR-PCell may then depend on processing of other PCells or other elements of a circuit design. Similarly, an FR-PCell may provide context information to other FR-PCells. In some embodiments, processing of an FR-PCell to generate an instance of the FR-PCell is managed by a reaction engine that monitors updates to context information or other PCells to automatically adjust instances of the FR-PCells.

公开(公告)号：US10460066B1

公开(公告)日：2019-10-29

申请号：US15649443

申请日：2017-07-13

Applicant: Cadence Design Systems, Inc.

Inventor： Gracieli Posser ,  Wen-Hao Liu ,  Wing-Kai Chow ,  Mehmet Can Yildiz ,  Zhuo Li

IPC: G06F17/50

Abstract: Aspects of the present disclosure address improved systems and methods for resolving single-entry constraint violations in hierarchical integrated circuit designs. In routing multi-pin nets of IC designs, the system employs a partition-entry-aware search algorithm to identify single-entry-violation-free routing results for two-pin nets, which are then combined to form routed multi-pin nets. The search algorithm is “entry-aware” in that it penalizes multiple entries into a single partition. Consistent with some embodiments, the system may further employ a post fix stage to remove extra partition entries for the multi-pin nets with single-entry violations by choosing a main entry to enter a partition and rerouting the paths that cause the violations such that the paths share the main entry.

公开(公告)号：US10460059B1

公开(公告)日：2019-10-29

申请号：US14747872

申请日：2015-06-23

Applicant: Cadence Design Systems, Inc.

Inventor： Akash Khandelwal ,  Pawan Kulshreshtha ,  Rajarshi Mukherjee ,  Chih-kuo Yu

IPC: G06F17/50 ,  G01R31/317

Abstract: A system and method for generating standard delay format (SDF) files is disclosed. For each timing closed hierarchical instance, timing arcs on internal register to register paths may be marked as zero delay arcs. If the zero delay causes a hold violation, an adjustment may be computed to fix the violation. If the adjustment does not cause a setup violation, the adjustment may be applied to the end point register.

公开(公告)号：US10460055B1

公开(公告)日：2019-10-29

申请号：US15955497

申请日：2018-04-17

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Yuvaraj Gogoi ,  Bhuvnesh Kumar ,  Anshu Mani ,  Suketu Desai

IPC: G06F17/50

Abstract: A computer performing a transient vectorless power analysis of a multi-clock domain integrated circuit (IC) design may execute a scheduling cycle based on the dominant clock frequency and schedule events based on comparing instance clock frequencies with the dominant clock frequency. If the instance clock frequency matches the dominant clock frequency, the computer may schedule a single event per scheduling cycle for the sequential circuit devices driven by the respective instance clocks. If the instance clock frequency is faster than the dominant clock frequency, the computer may schedule number of events per scheduling cycle based on the ratio of the instance clock frequency to the dominant clock frequency. If the instance clock frequency is less than the dominant clock frequency, the computer may schedule a single event per scheduling cycle if the computer determines that there is a triggering edge of the instance clock within the scheduling cycle.