公开(公告)号：US20050092996A1

公开(公告)日：2005-05-05

申请号：US10978512

申请日：2004-11-02

申请人： Shunpei Yamazaki ,  Hideomi Suzawa ,  Yoshihiro Kusuyama ,  Koji Ono ,  Jun Koyama

发明人： Shunpei Yamazaki ,  Hideomi Suzawa ,  Yoshihiro Kusuyama ,  Koji Ono ,  Jun Koyama

IPC分类号： H01L29/786 ,  G02F1/1362 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/04

CPC分类号： H01L21/4846 ,  G02F1/13454 ,  G02F1/13458 ,  G02F1/136286 ,  G02F2001/13629 ,  G02F2001/136295 ,  H01L21/02367 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1277 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/78621 ,  H01L29/78627

摘要： There are provided a structure of a semiconductor device in which low power consumption is realized even in a case where a size of a display region is increased to be a large size screen and a manufacturing method thereof. A gate electrode in a pixel portion is formed as a three layered structure of a material film containing mainly W, a material film containing mainly Al, and a material film containing mainly Ti to reduce a wiring resistance. A wiring is etched using an IPC etching apparatus. The gate electrode has a taper shape and the width of a region which becomes the taper shape is set to be 1 μm or more.

摘要翻译： 提供了即使在将显示区域的尺寸增加到大尺寸屏幕的情况下也实现低功耗的半导体器件的结构及其制造方法。 像素部分中的栅电极形成为主要包含W的材料膜，主要包含Al的材料膜和主要包含Ti的材料膜以降低布线电阻的三层结构。 使用IPC蚀刻装置蚀刻布线。 栅电极为锥形，成为锥形的区域的宽度为1um以上。

公开(公告)号：US20050029519A1

公开(公告)日：2005-02-10

申请号：US10941823

申请日：2004-09-16

申请人： Shunpei Yamazaki ,  Kiyoshi Kato ,  Atsuo Isobe ,  Hidekazu Miyairi ,  Hideomi Suzawa ,  Yutaka Shionoiri ,  Hiroyuki Miyake

发明人： Shunpei Yamazaki ,  Kiyoshi Kato ,  Atsuo Isobe ,  Hidekazu Miyairi ,  Hideomi Suzawa ,  Yutaka Shionoiri ,  Hiroyuki Miyake

IPC分类号： H01L21/20 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L29/04

CPC分类号： H01L21/02609 ,  H01L21/2026 ,  H01L27/12 ,  H01L27/1281 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78675 ,  H01L29/78696

摘要： A semiconductor element which is capable of operating at a high speed, high in an electric current drive capability, and small in fluctuation among a plurality of elements, and a semiconductor device including the semiconductor element are provided. The semiconductor element has a first crystalline semiconductor region including plural crystal orientations without practically having a grain boundary on an insulating surface, the first crystalline semiconductor region being provided to be jointly connected to a conductive region including the first crystalline semiconductor region and a second crystalline semiconductor region, in which the conductive region is provided astride insulating films extending in a linear stripe pattern.

摘要翻译： 提供能够高速运行，电流驱动能力高，多个元件之间波动小的半导体元件，以及包括半导体元件的半导体器件。 半导体元件具有包括多个晶体取向的第一晶体半导体区域，而绝缘表面实际上不具有晶界，第一晶体半导体区域被设置为共同连接到包括第一晶体半导体区域的导电区域和第二晶体半导体区域 区域，其中导电区域被设​​置成跨过线性条纹图案延伸的绝缘膜。

公开(公告)号：US06743649B2

公开(公告)日：2004-06-01

申请号：US10337704

申请日：2003-01-07

申请人： Shunpei Yamazaki ,  Hideomi Suzawa ,  Koji Ono ,  Yasuyuki Arai

发明人： Shunpei Yamazaki ,  Hideomi Suzawa ,  Koji Ono ,  Yasuyuki Arai

IPC分类号： H01L2100

CPC分类号： H01L27/1222 ,  G02F1/13454 ,  H01L21/32136 ,  H01L27/1237 ,  H01L27/124 ,  H01L27/127 ,  H01L27/1277 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78627 ,  H01L29/78645 ,  H01L2029/7863

摘要： By providing appropriate TFT structures arranged in various circuits of the semiconductor device in response to the functions required by the circuits, it is made possible to improve the operating performances and the reliability of a semiconductor device, reduce power consumption as well as realizing reduced manufacturing cost and increase in yield by lessening the number of processing steps. An LDD region of a TFT is formed to have a concentration gradient of an impurity element for controlling conductivity which becomes higher as the distance from a drain region decreases. In order to form such an LDD region having a concentration gradient of an impurity element, the present invention uses a method in which a gate electrode having a taper portion is provided to thereby dope an ionized impurity element for controlling conductivity accelerated in the electric field so that it penetrates through the gate electrode and a gate insulating film into a semiconductor layer.

公开(公告)号：US06739931B2

公开(公告)日：2004-05-25

申请号：US09953765

申请日：2001-09-17

申请人： Shunpei Yamazaki ,  Hideomi Suzawa ,  Ichiro Uehara

发明人： Shunpei Yamazaki ,  Hideomi Suzawa ,  Ichiro Uehara

IPC分类号： H05B3310

CPC分类号： H01L27/323 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/3246 ,  Y10S428/917

摘要： In an EL element having an anode, an insulating film (bump) formed on the anode, and an EL film and a cathode formed on the insulating film, each of a bottom end portion and a top end portion of the insulating film is formed so as to have a curved surface. The taper angle of a central portion of the insulating film is set within the range from 35° to 70°, thereby preventing the gradient of the film forming surface on which the EL film and the cathode are to be formed from being abruptly changed. On the thus-formed film forming surface, the EL film and the cathode can be formed so as to be uniform in thickness, so that occurrence of discontinuity in each of EL film and the cathode is prevented.

公开(公告)号：US06583471B1

公开(公告)日：2003-06-24

申请号：US09583678

申请日：2000-05-31

申请人： Shunpei Yamazaki ,  Hideomi Suzawa ,  Hirokazu Yamagata

发明人： Shunpei Yamazaki ,  Hideomi Suzawa ,  Hirokazu Yamagata

IPC分类号： H01L2701

CPC分类号： H01L29/78621 ,  G02F1/13454 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/3244 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/66765 ,  H01L29/78645 ,  H01L29/78675 ,  H01L29/78678 ,  H01L2924/0002 ,  H01L2924/00

摘要： In order to increase an aperture ratio, a part of or all of a gate electrode that overlaps with channel formation regions (213, 214) of a pixel TFT is caused to overlap with second wirings (source line or drain line) (154, 157). Additionally, a first interlayer insulating film (149) and a second interlayer insulating film (150c) are disposed between the gate electrode and the second wirings (154, 157) so as to decrease a parasitic capacitance.

摘要翻译： 为了增加开口率，与像素TFT的沟道形成区域（213,214）重叠的栅电极的一部分或全部与第二布线（源极线或漏极线）（154,157）重叠 ）。 此外，在栅电极和第二布线（154,157）之间设置第一层间绝缘膜（149）和第二层间绝缘膜（150c），以减小寄生电容。

公开(公告)号：US06515336B1

公开(公告)日：2003-02-04

申请号：US09664359

申请日：2000-09-18

申请人： Hideomi Suzawa ,  Koji Ono ,  Hideto Ohnuma ,  Hirokazu Yamagata ,  Shunpei Yamazaki

发明人： Hideomi Suzawa ,  Koji Ono ,  Hideto Ohnuma ,  Hirokazu Yamagata ,  Shunpei Yamazaki

IPC分类号： H01L2904

CPC分类号： G02F1/13454 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/42384 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78633 ,  H01L29/78645 ,  H01L2029/7863

摘要： TFTs arranged in various circuits have structures that are suited for circuit functions, in order to improve operation characteristics and reliability of the semiconductor device, to lower consumption of electric power, to decrease the number of steps, to lower the cost of production and to improve the yield. The gradient of concentration of impurity element for controlling the conduction type in the LDD regions 622 and 623 of the TFT is such that the concentration increases toward the drain region. For this purpose, a tapered gate electrode 607 and a tapered gate-insulating film 605 are formed, and the ionized impurity element for controlling the conduction type is added to the semiconductor layer through the gate-insulating film 605.

摘要翻译： 布置在各种电路中的TFT具有适于电路功能的结构，以便提高半导体器件的操作特性和可靠性，降低电力消耗，减少步数，降低生产成本和改善 产量。 用于控制TFT的LDD区域622和623中的导电类型的杂质元素的浓度梯度使得浓度朝着漏极区增加。 为此，形成锥形栅电极607和锥形栅极绝缘膜605，并且用于控制导电类型的电离杂质元件通过栅极绝缘膜605添加到半导体层。

公开(公告)号：US06433361B1

公开(公告)日：2002-08-13

申请号：US08999703

申请日：1997-02-05

申请人： Hongyong Zhang ,  Akira Takenouchi ,  Hideomi Suzawa

发明人： Hongyong Zhang ,  Akira Takenouchi ,  Hideomi Suzawa

IPC分类号： H01L2904

CPC分类号： H01L27/1214

摘要： In forming a thin film transistor (TFT), a semiconductor region is formed on a glass substrate and then a gate electrode is formed on the semiconductor region through an gate insulating film. After the gate electrode and a gate electrode arrangement extended from the gate electrode is anodized, insulators each having approximately rectangular shape are formed on side surfaces of the gate electrode and the gate electrode arrangement. An interlayer insulator is formed on a whole surface, and then the second layer arrangement is formed on the interlayer insulator. In an overlap portion in which the second layer arrangement overlaps the gate electrode and the gate electrode arrangement, since the insulators is formed, a slope is small.

摘要翻译： 在形成薄膜晶体管（TFT）时，在玻璃基板上形成半导体区域，然后通过栅极绝缘膜在半导体区域上形成栅电极。 在从栅电极延伸的栅极电极和栅极电极被阳极氧化之后，在栅电极和栅电极装置的侧表面上形成各自具有大致矩形形状的绝缘体。 在整个表面上形成层间绝缘体，然后在层间绝缘体上形成第二层布置。 在其中第二层布置与栅电极和栅电极布置重叠的重叠部分中，由于形成了绝缘体，所以斜率小。

公开(公告)号：US5914498A

公开(公告)日：1999-06-22

申请号：US450953

申请日：1995-05-23

申请人： Hideomi Suzawa ,  Yasuhiko Takemura

发明人： Hideomi Suzawa ,  Yasuhiko Takemura

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L29/76

CPC分类号： H01L29/78636 ,  H01L27/12 ,  H01L27/1244 ,  H01L27/1248 ,  Y10S257/90

摘要： A semiconductor integrated circuit comprising thin-film transistors in each of which the second wiring is prevented from breaking at steps. A silicon nitride film is formed on gate electrodes and on gate wiring extending from the gate electrodes. Substantially triangular regions are formed out of an insulator over side surfaces of the gate electrodes and of the gate wiring. The presence of these substantially triangular side walls make milder the steps at which the second wiring goes over the gate wiring. This suppresses breakage of the second wiring.

公开(公告)号：US5728259A

公开(公告)日：1998-03-17

申请号：US545122

申请日：1995-10-19

申请人： Hideomi Suzawa ,  Shunpei Yamazaki ,  Toshiji Hamatani ,  Yasuhiko Takemura

发明人： Hideomi Suzawa ,  Shunpei Yamazaki ,  Toshiji Hamatani ,  Yasuhiko Takemura

IPC分类号： H01L21/302 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/336 ,  H01L29/786

CPC分类号： H01L21/02057 ,  H01L21/30608 ,  H01L21/3065 ,  Y10S438/978 ,  Y10S438/98

摘要： Disclosed herein is a process for fabricating a thin-film semiconductor device which includes (1) a step of etching a silicon film by wet etching or gas etching, the former employing a liquid containing hydrazine or ethylene diamine, the latter employing chlorine fluoride, thereby forming an island-like silicon semiconductor region having inclined edges, and (2) a step of forming thereon a gate insulating film by plasma-free process such as heated CVD. The process yields the island-like silicon region and gate insulating film completely free from plasma-induced damage. This reduces the leakage current between the source and drain (which is due to plasma-induced damage) and prevents the degradation of characteristic properties.

摘要翻译： 本文公开了一种制造薄膜半导体器件的方法，其包括（1）通过湿蚀刻或气蚀刻蚀硅膜的步骤，前者采用含有肼或乙二胺的液体，后者采用氯氟化物 形成具有倾斜边缘的岛状硅半导体区域，以及（2）通过无等离子体工艺（例如加热CVD）在其上形成栅极绝缘膜的步骤。 该工艺使岛状硅区和栅极绝缘膜完全没有等离子体引起的损伤。 这减少了源极和漏极之间的泄漏电流（这是由于等离子体引起的损坏），并且防止了特性的降低。

公开(公告)号：US5641380A

公开(公告)日：1997-06-24

申请号：US566175

申请日：1995-12-01

申请人： Shunpei Yamazaki ,  Hideomi Suzawa ,  Yasuhiko Takemura

发明人： Shunpei Yamazaki ,  Hideomi Suzawa ,  Yasuhiko Takemura

IPC分类号： H01L21/302 ,  H01L21/3213 ,  H01L21/336 ,  H01L29/78 ,  H01L21/00

CPC分类号： H01L29/6659 ,  H01L21/32137

摘要： There is proposed a process for performing (quasi-) anisotropic etching on a silicon-based material without using plasma. The process consists of irradiating a polycrystalline or single-crystalline silicon film or substrate with a beam of accelerated hydrogen ions, silicon ions, or rare gas ions, so that the crystalline silicon is made amorphous. Then, the amorphous silicon is placed in an atmosphere of fluorinated halogen. Since the etching rate of fluorinated halogen for amorphous silicon is greater than that for polycrystalline or single-crystalline silicon, etching takes place selectively at the area which has been irradiated with a beam of accelerated hydrogen ions, silicon ions, or rare gas ions. The selective etching permits (quasi-) anisotropic etching instead of sideward isotropic etching.

摘要翻译： 提出了在不使用等离子体的情况下对硅基材料进行（准）各向异性蚀刻的方法。 该方法包括用加速的氢离子，硅离子或稀有气体离子的束照射多晶或单晶硅膜或衬底，使得晶体硅是无定形的。 然后，将非晶硅置于氟化卤素气氛中。 由于非晶硅的氟化卤素的蚀刻速率大于多晶或单晶硅的蚀刻速率，所以在已经用加速的氢离子，硅离子或稀有气体离子的束照射的区域上选择性地进行蚀刻。 选择性蚀刻允许（准）各向异性蚀刻而不是侧向各向同性蚀刻。