公开(公告)号：US20140231923A1

公开(公告)日：2014-08-21

申请号：US14346537

申请日：2012-05-16

Applicant: Huaxiang Yin ,  Qiuxia Xu ,  Dapeng Chen

Inventor： Huaxiang Yin ,  Qiuxia Xu ,  Dapeng Chen

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/76232 ,  H01L21/823807 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7846 ,  H01L29/7848

Abstract: The present invention provides a semiconductor structure, comprising: a substrate; a gate stack located on the substrate and comprising at least a gate dielectric layer and a gate electrode layer; source/drain regions, located in the substrate on both sides of the gate stack; an STI structure, located in the substrate on both sides of the source/drain regions, wherein the cross-section of the STI structure is trapezoidal, Sigma-shaped or inverted trapezoidal depending on the type of the semiconductor structure. Correspondingly, the present invention further to provides a method of manufacturing the semiconductor structure. In the present invention, STI structures having different shapes can be combined with different stress fillers to apply tensile stress or compressive stress laterally to the channel, which will produce a positive impact on the electron mobility of NMOS and the hole mobility of PMOS and increase the channel current of the device, thereby effectively improving the performance of the semiconductor structure.

Abstract translation: 本发明提供一种半导体结构，包括：基板; 位于所述基板上并且至少包括栅极电介质层和栅极电极层的栅极堆叠; 源极/漏极区域，位于栅极堆叠两侧的衬底中; STI结构，位于源极/漏极区两侧的衬底中，其中根据半导体结构的类型，STI结构的横截面为梯形，Σ形或倒梯形。 相应地，本发明还提供一种制造半导体结构的方法。 在本发明中，具有不同形状的STI结构可以与不同的应力填料组合以向沟道侧向施加拉伸应力或压应力，这将对NMOS的电子迁移率和PMOS的空穴迁移率产生积极影响，并增加 通道电流，从而有效地提高了半导体结构的性能。

公开(公告)号：US20140197376A1

公开(公告)日：2014-07-17

申请号：US13812504

申请日：2012-10-12

Applicant: Xiaolong Ma ,  Huaxiang Yin ,  Sen Xu ,  Huilong Zhu

Inventor： Xiaolong Ma ,  Huaxiang Yin ,  Sen Xu ,  Huilong Zhu

IPC: H01L29/775

CPC classification number: H01L29/775 ,  H01L29/161 ,  H01L29/165 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66431 ,  H01L29/66545 ,  H01L29/7786

Abstract: The present invention discloses a semiconductor device, which comprises a substrate, a buffer layer on the substrate, an inversely doped isolation layer on the buffer layer, a barrier layer on the inversely doped isolation layer, a channel layer on the barrier layer, a gate stack structure on the channel layer, and source and drain regions at both sides of the gate stack structure, characterized in that the buffer layer and/or the barrier layer and/or the inversely doped isolation layer are formed of SiGe alloys or SiGeSn alloys, and the channel layer is formed of a GeSn alloy. The semiconductor device according to the present invention uses a quantum well structure of SiGe/GeSn/SiGe to restrict transportation of carriers, and it introduces a stress through lattice mis-match to greatly increase the carrier mobility, thus improving the device driving capability so as to be adapted to high-speed and high-frequency application.

Abstract translation: 本发明公开了一种半导体器件，其包括衬底，衬底上的缓冲层，缓冲层上的反掺杂隔离层，反掺杂隔离层上的阻挡层，阻挡层上的沟道层，栅极 沟道层上的堆叠结构以及栅极堆叠结构两侧的源极和漏极区域，其特征在于缓冲层和/或势垒层和/或反向掺杂隔离层由SiGe合金或SiGeSn合金形成， 并且沟道层由GeSn合金形成。 根据本发明的半导体器件使用SiGe / GeSn / SiGe的量子阱结构来限制载流子的传输，并且通过晶格失配引入应力以大大增加载流子迁移率，从而提高器件驱动能力，从而 适应高速高频应用。

公开(公告)号：US08716090B2

公开(公告)日：2014-05-06

申请号：US13580962

申请日：2012-06-12

Applicant: Changliang Qin ,  Huaxiang Yin

Inventor： Changliang Qin ,  Huaxiang Yin

IPC: H01L21/336

CPC classification number: H01L29/165 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

Abstract: The present invention provides a manufacturing method for a semiconductor device having epitaxial source/drain regions, in which a diffusion barrier layer of the source/drain regions made of epitaxial silicon-carbon or germanium silicon-carbon are added on the basis of epitaxially growing germanium-silicon of the source/drain regions in the prior art process, and the introduction of the diffusion barrier layer of the source/drain regions prevents diffusion of the dopant in the source/drain regions, thus mitigating the SCE and DIBL effect. The use of the diffusion barrier layer for the source/drain regions can also reduce the dosage of HALO implantation in the subsequent step, thus if HALO is performed before epitaxial growth of the source/drain regions, impact on the surfaces of the source/drain regions can be alleviated; if HALO is performed after epitaxial growth of the source/drain regions, the stress release effect of the epitaxial layer of the source drain/regions caused by the implantation can be reduced as much as possible.

Abstract translation: 本发明提供了一种具有外延源极/漏极区域的半导体器件的制造方法，其中基于外延生长锗添加由外延硅 - 碳或锗硅 - 碳制成的源极/漏极区的扩散阻挡层 在现有技术的工艺中源极/漏极区域的硅，以及源极/漏极区域的扩散阻挡层的引入防止了掺杂剂在源/漏区域中的扩散，从而减轻了SCE和DIBL效应。 用于源极/漏极区域的扩散阻挡层的使用也可以降低后续步骤中的HALO注入的剂量，因此如果在源极/漏极区域的外延生长之前执行HALO，则冲击源极/漏极 地区可以缓解; 如果在源/漏区的外延生长之后执行HALO，则可以尽可能地减少由注入引起的源漏极/区域的外延层的应力释放效应。

公开(公告)号：US20140120719A1

公开(公告)日：2014-05-01

申请号：US13812505

申请日：2012-10-12

Applicant: Changliang Qin ,  Huaxiang Yin

Inventor： Changliang Qin ,  Huaxiang Yin

IPC: H01L21/3213

CPC classification number: H01L21/32139 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28123

Abstract: The present invention relates to a method of manufacturing a semiconductor device for improving the spacer mask. In the present invention, a barrier layer and a sacrificial layer are formed, and the portions of the upper part of the spacer whose left and right sides differ greatly are ground away to leave the portion similar to a rectangle at the bottom of the spacer, which is used as the mask to perform the subsequent spacer masking technology. Thus the undesirable influences to the subsequent etching caused by the asymmetric profile of the spacer can be reduced as much as possible.

Abstract translation: 本发明涉及一种制造用于改进间隔掩模的半导体器件的方法。 在本发明中，形成了阻挡层和牺牲层，并且左右两侧的差异较大的间隔物的上部的部分被磨去，使其与垫片底部的长方形相似， 其用作掩模以执行后续间隔物掩蔽技术。 因此，可以尽可能地减少由间隔物的不对称轮廓引起的对随后的蚀刻的不良影响。

公开(公告)号：US20130241004A1

公开(公告)日：2013-09-19

申请号：US13520618

申请日：2012-04-11

Applicant: Huaxiang Yin ,  Zuozhen Fu ,  Qiuxia Xu ,  Chao Zhao ,  Dapeng Chen

Inventor： Huaxiang Yin ,  Zuozhen Fu ,  Qiuxia Xu ,  Chao Zhao ,  Dapeng Chen

IPC: H01L27/088 ,  H01L21/8236

CPC classification number: H01L21/823807 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/7845

Abstract: The present invention discloses a semiconductor device, comprising substrates, a plurality of gate stack structures on the substrate, a plurality of gate spacer structures on both sides of each gate stack structure, a plurality of source and drain regions in the substrate on both sides of each gate spacer structure, the plurality of gate spacer structures comprising a plurality of first gate stack structures and a plurality of second gate stack structures, wherein each of the first gate stack structures comprises a first gate insulating layer, a first work function metal layer, a second work function metal diffusion blocking layer, and a gate filling layer; Each of the second gate stack structures comprises a second gate insulating layer, a first work function metal layer, a second work function metal layer, and a gate filling layer, characterized in that the first work function metal layer has a first stress, and the gate filling layer has a second stress. Two metal gate layers of different types and/or intensity of stress are formed, respectively, thus different stresses are applied to the channel regions of different MOSFETs effectively and accurately, the device carrier mobility is enhanced simply and efficiently, and the device performance is also enhanced.

Abstract translation: 本发明公开了一种半导体器件，包括衬底，衬底上的多个栅极堆叠结构，在每个栅极堆叠结构的两侧上的多个栅极间隔结构，在衬底的两侧的多个源极和漏极区域 每个栅极间隔结构，所述多个栅极间隔结构包括多个第一栅极堆叠结构和多个第二栅极堆叠结构，其中所述第一栅极堆叠结构中的每一个包括第一栅极绝缘层，第一功函数金属层， 第二功函数金属扩散阻挡层和栅极填充层; 每个第二栅极堆叠结构包括第二栅极绝缘层，第一功函数金属层，第二功函数金属层和栅极填充层，其特征在于，第一功函数金属层具有第一应力，并且 栅极填充层具有第二应力。 形成不同类型和/或应力强度的两个金属栅极层，从而有效且准确地对不同MOSFET的沟道区域施加不同的应力，简单高效地提高器件载流子迁移率，器件性能也是 增强。

公开(公告)号：US20130221535A1

公开(公告)日：2013-08-29

申请号：US13517050

申请日：2012-02-29

Applicant: Xiaolong Ma ,  Huaxiang Yin ,  Lichuan Zhao

Inventor： Xiaolong Ma ,  Huaxiang Yin ,  Lichuan Zhao

IPC: H01L23/48 ,  B32B9/00 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10T428/30 ,  H01L2924/00

Abstract: A diffusion barrier layer, a metal interconnect arrangement and a method of manufacturing the same are disclosed. In one embodiment, the metal interconnect arrangement may comprise a conductive plug/interconnect wire for electrical connection, and a diffusion barrier layer provided on at least a portion of a surface of the conductive plug/interconnect wire. The diffusion barrier layer may comprise insulating amorphous carbon.

Abstract translation: 公开了一种扩散阻挡层，金属互连装置及其制造方法。 在一个实施例中，金属互连装置可以包括用于电连接的导电插头/互连线，以及设置在导电插头/互连线的表面的至少一部分上的扩散阻挡层。 扩散阻挡层可以包括绝缘无定形碳。

公开(公告)号：US08405062B2

公开(公告)日：2013-03-26

申请号：US11713738

申请日：2007-03-05

Applicant: Huaxiang Yin ,  Young-soo Park ,  Wenxu Xianyu ,  Hans S. Cho

Inventor： Huaxiang Yin ,  Young-soo Park ,  Wenxu Xianyu ,  Hans S. Cho

IPC: H01L47/00

CPC classification number: H01L21/02686 ,  H01L21/02532 ,  H01L21/2026 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146

Abstract: A method of forming a poly-silicon pattern may include forming an amorphous silicon pattern on a lower layer; forming a capping layer on the substrate covering the amorphous silicon pattern; poly-crystallizing the amorphous silicon pattern using an excimer laser annealing process; and removing the capping layer.

Abstract translation: 形成多晶硅图案的方法可以包括在下层上形成非晶硅图案; 在覆盖所述非晶硅图案的所述基板上形成覆盖层; 使用准分子激光退火工艺多晶结晶非晶硅图案; 并去除覆盖层。

公开(公告)号：US08383472B2

公开(公告)日：2013-02-26

申请号：US13067306

申请日：2011-05-24

Applicant: Huaxiang Yin ,  I-hun Song ,  Chang-jung Kim ,  Sang-wook Kim ,  Sun-il Kim

Inventor： Huaxiang Yin ,  I-hun Song ,  Chang-jung Kim ,  Sang-wook Kim ,  Sun-il Kim

IPC: H01L21/336

CPC classification number: H01L21/823807 ,  H01L27/0922 ,  H01L27/1225 ,  H01L27/1251

Abstract: Provided are an inverter, a method of manufacturing the inverter, and a logic circuit including the inverter. The inverter may include a first transistor and a second transistor having different channel layer structures. A channel layer of the first transistor may include a lower layer and an upper layer, and a channel layer of the second transistor may be the same as one of the lower layer and the upper layer. At least one of the lower layer and the upper layer may be an oxide layer. The inverter may be an enhancement/depletion (E/D) mode inverter or a complementary inverter.

Abstract translation: 提供逆变器，逆变器的制造方法以及包括逆变器的逻辑电路。 反相器可以包括具有不同沟道层结构的第一晶体管和第二晶体管。 第一晶体管的沟道层可以包括下层和上层，并且第二晶体管的沟道层可以与下层和上层之一相同。 下层和上层中的至少一层可以是氧化物层。 逆变器可以是增强/耗尽型（E / D）型逆变器或互补型逆变器。

公开(公告)号：US08097499B2

公开(公告)日：2012-01-17

申请号：US11702624

申请日：2007-02-06

Applicant: Wenxu Xianyu ,  Young-soo Park ,  Jun-ho Lee ,  Hyuk Lim ,  Hans S. Cho ,  Huaxiang Yin

Inventor： Wenxu Xianyu ,  Young-soo Park ,  Jun-ho Lee ,  Hyuk Lim ,  Hans S. Cho ,  Huaxiang Yin

IPC: H01L21/00 ,  H01L21/84

CPC classification number: H01L21/02609 ,  H01L21/02381 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02516 ,  H01L21/02532

Abstract: A semiconductor device and method thereof. The example method may include forming a semiconductor device, including forming a first layer on a substrate, the first layer including aluminum nitride (AlN), forming a second layer by oxidizing a surface of the first layer and forming a third layer on the second layer, the first, second and third layers each being highly oriented with respect to one of a plurality crystallographic planes. The example semiconductor device may include a substrate including a first layer, the first layer including aluminum nitride (AlN), a second layer formed by oxidizing a surface of the first layer and a third layer formed on the second layer, the first, second and third layers each being highly oriented with respect to one of a plurality crystallographic planes.

Abstract translation: 半导体器件及其方法。 示例性方法可以包括形成半导体器件，包括在衬底上形成第一层，第一层包括氮化铝（AlN），通过氧化第一层的表面并在第二层上形成第三层来形成第二层 ，第一层，第二层和第三层各自相对于多个晶面之一高度取向。 示例性半导体器件可以包括：衬底，其包括第一层，第一层包括氮化铝（AlN），通过氧化第一层的表面形成的第二层和形成在第二层上的第三层，第一层，第二层和第二层 第三层各自相对于多个晶面之一高度取向。

公开(公告)号：US07994588B2

公开(公告)日：2011-08-09

申请号：US12073398

申请日：2008-03-05

Applicant: Huaxiang Yin ,  Young-soo Park ,  Sun-Il Kim

Inventor： Huaxiang Yin ,  Young-soo Park ,  Sun-Il Kim

IPC: H01L21/70

CPC classification number: H01L27/115 ,  H01L21/84 ,  H01L27/11521 ,  H01L27/1203

Abstract: Example embodiments provide a nonvolatile memory device that may be integrated through stacking, a stack module, and a method of fabricating the nonvolatile memory device. In the nonvolatile memory device according to example embodiments, at least one bottom gate electrode may be formed on a substrate. At least one charge storage layer may be formed on the at least one bottom gate electrode, and at least one semiconductor channel layer may be formed on the at least one charge storage layer.

Abstract translation: 示例性实施例提供了可以通过堆叠集成的非易失性存储器件，堆叠模块和制造非易失性存储器件的方法。 在根据示例性实施例的非易失性存储器件中，可以在衬底上形成至少一个底栅电极。 至少一个电荷存储层可以形成在至少一个底栅电极上，并且至少一个半导体沟道层可以形成在至少一个电荷存储层上。