公开(公告)号：US20080233686A1

公开(公告)日：2008-09-25

申请号：US12113803

申请日：2008-05-01

Applicant: Jian-Hsing LEE ,  Deng-Shun Chang

Inventor： Jian-Hsing LEE ,  Deng-Shun Chang

IPC: H01L21/332

CPC classification number: H01L27/0277 ,  H01L27/0255

Abstract: An electrostatic discharge (ESD) protection device includes a diode located in a substrate and an N-type metal oxide semiconductor (NMOS) device located in the substrate adjacent the diode, wherein both the diode and the NMOS are coupled to an input device, and at least a portion of the diode and at least a portion of the NMOS device collectively form an ESD protection device.

Abstract translation: 静电放电（ESD）保护装置包括位于衬底中的二极管和位于与二极管相邻的衬底中的N型金属氧化物半导体（NMOS）器件，其中二极管和NMOS都耦合到输入器件，以及 二极管的至少一部分和NMOS器件的至少一部分共同形成ESD保护器件。

公开(公告)号：US07405445B2

公开(公告)日：2008-07-29

申请号：US10887793

申请日：2004-07-09

Applicant: Shao-Chang Huang ,  Jian-Hsing Lee

Inventor： Shao-Chang Huang ,  Jian-Hsing Lee

IPC: H01L23/62

CPC classification number: H01L27/0255 ,  H01L27/0814 ,  H01L29/0619

Abstract: A semiconductor integrated circuit structure includes a plurality of diodes disposed in the substrate. These diodes are electrically coupled in series. At least one insertion region is disposed in the substrate between two of the diodes and a supply voltage node electrically coupled to the insertion region. Preferably, a guard ring surrounds the diodes.

Abstract translation: 半导体集成电路结构包括设置在基板中的多个二极管。 这些二极管串联电耦合。 至少一个插入区域设置在两个二极管之间的衬底中，以及电耦合到插入区域的电源电压节点。 优选地，保护环围绕二极管。

公开(公告)号：US20080128818A1

公开(公告)日：2008-06-05

申请号：US11606424

申请日：2006-11-30

Applicant: Shui-Hung Chen ,  Jian-Hsing Lee ,  Yi-Hsun Wu ,  D. J. Perng ,  Anthony Oates

Inventor： Shui-Hung Chen ,  Jian-Hsing Lee ,  Yi-Hsun Wu ,  D. J. Perng ,  Anthony Oates

IPC: H01L27/06

CPC classification number: H01L29/0847 ,  H01L27/0266 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/7816 ,  H01L29/7835

Abstract: An electrostatic discharge-protected MOS structure is disclosed. An electrostatic discharge-protected MOS structure includes a semiconductor substrate of a first type, a first well of the first type formed in the semiconductor substrate, and a second well of a second type disposed adjacent to the first well. The MOS structure further includes a source region, a drain region, and an oxide layer and a polysilicon layer for forming a gate electrode of the MOS structure. In addition, the MOS structure includes a parasitic SCR comprising at least a parasitic NPN bipolar transistor and a buried layer of the second type interposed between the second well and the semiconductor substrate. The buried layer functions to lower a resistance of the semiconductor substrate during an ESD event so that ESD currents generated by the parasitic SCR are dissipated through the buried layer and the semiconductor substrate, thereby protecting the MOS structure.

公开(公告)号：US07362555B2

公开(公告)日：2008-04-22

申请号：US11509998

申请日：2006-08-26

Applicant: Chau-Neng Wu ,  Jian-Hsing Lee

Inventor： Chau-Neng Wu ,  Jian-Hsing Lee

IPC: H02H9/00

CPC classification number: H02H9/046

Abstract: An ESD protection circuit is implemented for a semiconductor device having a first circuit system operating with a first power supply voltage and a first complementary power supply voltage, and a second circuit system operating with a second power supply voltage and a second complementary power supply voltage. The ESD protection circuit includes a first diode having an anode coupled to the first power supply voltage and a cathode coupled to a first node connecting the first circuit system and the second circuit system for preventing a crosstalk of current between the first power supply voltage and the second complementary power supply voltage. A first MOS transistor module is coupled between the first node and the first complementary power supply for selectively creating a current path from the first node to the first complementary supply voltage for dissipating an ESD current during an ESD event.

Abstract translation: 对具有以第一电源电压和第一互补电源电压工作的第一电路系统的半导体器件以及以第二电源电压和第二互补电源电压工作的第二电路系统实施ESD保护电路。 ESD保护电路包括具有耦合到第一电源电压的阳极的第一二极管和耦合到连接第一电路系统和第二电路系统的第一节点的阴极，用于防止第一电源电压和第二电源电压之间的电流串扰 第二互补电源电压。 第一MOS晶体管模块耦合在第一节点和第一互补电源之间，用于选择性地创建从第一节点到第一互补电源电压的电流路径，以在ESD事件期间耗散ESD电流。

公开(公告)号：US20080042207A1

公开(公告)日：2008-02-21

申请号：US11506948

申请日：2006-08-17

Applicant: Yi-Hsun Wu ,  Jian-Hsing Lee ,  Kuo-Feng Yu ,  C.S. Tang ,  Cheng-Chun Ting

Inventor： Yi-Hsun Wu ,  Jian-Hsing Lee ,  Kuo-Feng Yu ,  C.S. Tang ,  Cheng-Chun Ting

IPC: H01L23/62

CPC classification number: H01L23/60 ,  H01L24/06 ,  H01L27/0207 ,  H01L27/0266 ,  H01L29/41775 ,  H01L29/4238 ,  H01L2224/0401 ,  H01L2924/01082 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00

Abstract: A transistor layout is disclosed for improving electrostatic discharge capabilities. The layout has a first gate region with a first active region and a second active region formed on two sides thereof, and a second gate region placed next to the second active region with a third active region placed on an opposing side of the second gate region from the second active region. A first and a second set of contacts formed on the first and the third active regions, and a third set of contacts formed on the second active region, wherein the third set of contacts are spaced in parallel with and offset from the other two sets of contacts such that no contact from the third set is aligned laterally with a contact from either the first or the second set of contacts.

Abstract translation: 公开了用于改善静电放电能力的晶体管布局。 布局具有第一栅极区域，其具有形成在其两侧的第一有源区和第二有源区，以及放置在第二有源区旁边的第二栅极区，第三有源区位于第二栅极区的相对侧 从第二个活跃区域。 形成在第一和第三有源区上的第一和第二组触点，以及形成在第二有源区上的第三组触点，其中第三组触点与另外两组触点间隔开并偏离 触点，使得第三组的接触不与来自第一组或第二组触点的触点对齐。

公开(公告)号：US20080023766A1

公开(公告)日：2008-01-31

申请号：US11459650

申请日：2006-07-25

Applicant: Feng-Chi Hung ,  Jian-Hsing Lee ,  Hung-Lin Chen ,  Deng-Shun Chang

Inventor： Feng-Chi Hung ,  Jian-Hsing Lee ,  Hung-Lin Chen ,  Deng-Shun Chang

IPC: H01L23/62

CPC classification number: H01L29/0847 ,  H01L29/0692 ,  H01L29/7835

Abstract: An electrostatic discharge protection device comprising a multi-finger gate, a first lightly doped region of a second conductivity, a first heavily doped region of the second conductivity, and a second lightly doped region of the second conductivity. The multi-finger gate comprises a plurality of fingers mutually connected in parallel over an active region of a first conductivity. The first lightly doped region of a second conductivity is disposed in the semiconductor substrate and between two of the fingers. The first heavily doped region of the second conductivity is disposed in the first lightly doped region of the second conductivity. The second lightly doped region of the second conductivity is beneath and adjoins the first lightly doped region of the second conductivity.

Abstract translation: 一种静电放电保护装置，包括多指门，具有第二导电性的第一轻掺杂区，第二导电性的第一重掺杂区和第二导电性的第二轻掺杂区。 多指门包括在第一导电性的有源区域上并联连接的多个指状物。 第二导电性的第一轻掺杂区域设置在半导体衬底中并且在两个指状物之间。 第二导电性的第一重掺杂区域设置在第二导电性的第一轻掺杂区域中。 第二导电性的第二轻掺杂区域位于第二导电性的第一轻掺杂区域的下方并与其邻接。

公开(公告)号：US07309897B2

公开(公告)日：2007-12-18

申请号：US11402907

申请日：2006-04-13

Applicant: Kuo-Feng Yu ,  Jian-Hsing Lee ,  Juing-Yi Wu ,  Chong-Gim Gan ,  Dun-Nian Yaung

Inventor： Kuo-Feng Yu ,  Jian-Hsing Lee ,  Juing-Yi Wu ,  Chong-Gim Gan ,  Dun-Nian Yaung

IPC: H01L23/62

CPC classification number: H01L29/0847 ,  H01L23/60 ,  H01L27/0277 ,  H01L29/0692 ,  H01L29/41725 ,  H01L29/41758 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit has functional circuitry coupled to a terminal. An electrostatic discharge protector can be coupled to the terminal to protect the functional circuitry from an electrostatic discharge. A substrate includes a first semiconductor material with a first dopant type. A plurality of drain segments adjoin the substrate. Each of the drain segments has a first conductor, a second conductor, and a third conductor. A central via set in a central region of the drain segment couples the second conductor to the third conductor. A peripheral via set in a peripheral region of the drain segment couples the first conductor to the second conductor. A plurality of source segments adjoin the substrate and laterally interlace with the drain segments. If an electrostatic discharge is detected at the terminal of the integrated circuit, an electrical current of the ESD is directed into the electrostatic discharge protector and distributed substantially uniformly among a plurality of resistive paths in the electrostatic discharge protector.

Abstract translation: 集成电路具有耦合到终端的功能电路。 静电放电保护器可以耦合到端子以保护功能电路免受静电放电。 衬底包括具有第一掺杂剂类型的第一半导体材料。 多个漏极段邻接衬底。 每个漏极段具有第一导体，第二导​​体和第三导体。 设置在排水段的中心区域的中心通孔将第二导体连接到第三导体。 设置在漏极段的外围区域中的周边通孔将第一导体耦合到第二导体。 多个源区段与衬底相邻并与排水段横向交错。 如果在集成电路的端子处检测到静电放电，则ESD的电流被引导到静电放电保护器中并且基本均匀地分布在静电放电保护器中的多个电阻路径之中。

公开(公告)号：US07256975B2

公开(公告)日：2007-08-14

申请号：US10867112

申请日：2004-06-14

Applicant: Yi-Hsun Wu ,  Jian-Hsing Lee ,  Shui-Hung Chen

Inventor： Yi-Hsun Wu ,  Jian-Hsing Lee ,  Shui-Hung Chen

IPC: H02H9/00

CPC classification number: H03K17/08142 ,  H01L27/0266

Abstract: An electrostatic discharge (ESD) protection circuit and method thereof are presented. In some embodiments, a high voltage tolerant input/output circuit comprises an ESD detection circuit, a first first-type transistor, a first second-type transistor, and a second second-type transistor. The first first-type transistor and the first second-type transistor are coupled to a pad. The ESD detection circuit determines whether ESD occurs at the pad and, if so, couples the gates of the first and second second-type transistors to the second power rail.

Abstract translation: 提出了一种静电放电（ESD）保护电路及其方法。 在一些实施例中，高耐压输入/输出电路包括ESD检测电路，第一第一型晶体管，第一第二型晶体管和第二第二型晶体管。 第一第一型晶体管和第一第二型晶体管耦合到焊盘。 ESD检测电路确定ESD是否发生在焊盘处，如果是，则将第一和第二第二型晶体管的栅极耦合到第二电源轨。

公开(公告)号：US20070170469A1

公开(公告)日：2007-07-26

申请号：US11337147

申请日：2006-01-20

Applicant: Kuo-Ming Wu ,  Jian-Hsing Lee ,  Yi-Chun Lin ,  Chi-Chih Chen

Inventor： Kuo-Ming Wu ,  Jian-Hsing Lee ,  Yi-Chun Lin ,  Chi-Chih Chen

IPC: H01L29/76

CPC classification number: H01L29/7816 ,  H01L29/0696 ,  H01L29/0873 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/4238

Abstract: A semiconductor device includes a first doped region disposed on a first well in a semiconductor substrate; a second doped region disposed on a second well adjacent to the first well in the semiconductor substrate, the second doped region having a dopant density higher than that of the second well; and a gate structure overlying parts of the first and second wells for controlling a current flowing between the first and second doped regions. A first spacing distance from an interface between the second doped region and the second well to its closest edge of the gate structure is greater than 200 percent of a second spacing distance from a center point of second doped region to the edge of the gate structure, thereby increasing impedance against an electrostatic discharge (ESD) current flowing between the first and second doped regions during an ESD event.

Abstract translation: 半导体器件包括设置在半导体衬底中的第一阱上的第一掺杂区; 第二掺杂区域，其设置在与所述半导体衬底中的所述第一阱相邻的第二阱上，所述第二掺杂区域的掺杂剂密度高于所述第二阱的掺杂剂密度; 以及覆盖第一和第二阱的部分的栅极结构，用于控制在第一和第二掺杂区域之间流动的电流。 从第二掺杂区域和第二阱之间的界面到其栅极结构的最近边缘的第一间隔距离大于从第二掺杂区域的中心点到栅极结构边缘的第二间隔距离的200％ 从而增加针对在ESD事件期间在第一和第二掺杂区域之间流动的静电放电（ESD）电流的阻抗。

公开(公告)号：US07238969B2

公开(公告)日：2007-07-03

申请号：US11152440

申请日：2005-06-14

Applicant: Yi-Hsun Wu ,  Kuan-Lun Chang ,  Chuan-Ying Lee ,  Jian-Hsing Lee

Inventor： Yi-Hsun Wu ,  Kuan-Lun Chang ,  Chuan-Ying Lee ,  Jian-Hsing Lee

IPC: H01L29/72 ,  H01L29/74 ,  H01L31/111 ,  H01L23/62

CPC classification number: H01L27/0262

Abstract: A semiconductor layout structure for an electrostatic discharge (ESD) protection circuit is disclosed. The semiconductor layout structure includes a first area, in which one or more devices are constructed for functioning as a silicon controlled rectifier, and a second area, in which at least one device is constructed for functioning as a trigger source that provides a triggering current to trigger the silicon controlled rectifier for dissipating ESD charges during an ESD event. The first area and the second area are placed adjacent to one another without having a resistance area physically interposed or electrically connected therebetween, such that the triggering current received by the silicon controlled rectifier is increased during the ESD event.

Abstract translation: 公开了一种用于静电放电（ESD）保护电路的半导体布局结构。 半导体布局结构包括第一区域，其中构造一个或多个器件用作可控硅整流器，以及第二区域，其中构造至少一个器件用作触发源，该触发源提供触发电流 触发可控硅整流器，以在ESD事件期间耗散ESD电荷。 第一区域和第二区域彼此相邻放置，而不会在其间物理地插入或电连接电阻区域，使得在ESD事件期间由可控硅整流器接收的触发电流增加。