公开(公告)号：US20130307513A1

公开(公告)日：2013-11-21

申请号：US13976414

申请日：2011-12-19

Applicant: Han Wui Then ,  Robert Chau ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Jack Kavalieros ,  Matthew Metz ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Marko Radosavljevic

Inventor： Han Wui Then ,  Robert Chau ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Jack Kavalieros ,  Matthew Metz ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Marko Radosavljevic

IPC: H01L29/775 ,  G05F3/02 ,  H01L29/66

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  G05F3/02 ,  H01L21/02603 ,  H01L21/02636 ,  H01L21/225 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/31 ,  H01L21/31116 ,  H01L21/32133 ,  H01L21/324 ,  H01L29/04 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/2003 ,  H01L29/41725 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66462 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/78696

Abstract: Transistors suitable for high voltage and high frequency operation. A nanowire is disposed vertically or horizontally on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first semiconductor material, a source region electrically coupled with a first end of the channel region, a drain region electrically coupled with a second end of the channel region, and an extrinsic drain region disposed between the channel region and drain region. The extrinsic drain region has a wider bandgap than that of the first semiconductor. A gate stack including a gate conductor and a gate insulator coaxially wraps completely around the channel region, drain and source contacts similarly coaxially wrap completely around the drain and source regions.

Abstract translation: 晶体管适用于高电压和高频工作。 纳米线垂直或水平地布置在基底上。 纳米线的纵向长度被限定为第一半导体材料的沟道区域，与沟道区域的第一端电耦合的源极区域，与沟道区域的第二端电耦合的漏极区域和外部漏极 区域设置在沟道区域和漏极区域之间。 外在漏极区具有比第一半导体更宽的带隙。 包括栅极导体和栅极绝缘体的栅极堆叠器完全同轴地包裹在沟道区域周围，漏极和源极触点类似地同轴地围绕漏极和源极区域包裹。

公开(公告)号：US08183646B2

公开(公告)日：2012-05-22

申请号：US13021640

申请日：2011-02-04

Applicant: Robert S. Chau ,  Suman Datta ,  Jack Kavalieros ,  Justin K. Brask ,  Mark L. Doczy ,  Matthew Metz

Inventor： Robert S. Chau ,  Suman Datta ,  Jack Kavalieros ,  Justin K. Brask ,  Mark L. Doczy ,  Matthew Metz

IPC: H01L27/088

CPC classification number: H01L29/7848 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/20 ,  H01L29/201 ,  H01L29/207 ,  H01L29/267 ,  H01L29/41783 ,  H01L29/4236 ,  H01L29/452 ,  H01L29/517 ,  H01L29/66522 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7827 ,  H01L29/7836 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78681

Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.

Abstract translation: 描述具有窄带隙半导体源极/漏极区域的晶体管。 晶体管包括形成在形成于硅层上的栅介质层上的栅电极。 一对源极/漏极区域形成在栅电极的相对侧上，其中所述一对源极/漏极区域包括形成在栅电极的相对侧上的硅层中的窄带隙半导体膜。

公开(公告)号：US07893506B2

公开(公告)日：2011-02-22

申请号：US12850582

申请日：2010-08-04

Applicant: Robert S. Chau ,  Suman Datta ,  Jack Kavalieros ,  Justin K. Brask ,  Mark L. Doczy ,  Matthew Metz

Inventor： Robert S. Chau ,  Suman Datta ,  Jack Kavalieros ,  Justin K. Brask ,  Mark L. Doczy ,  Matthew Metz

IPC: H01L27/088

CPC classification number: H01L29/7848 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/20 ,  H01L29/201 ,  H01L29/207 ,  H01L29/267 ,  H01L29/41783 ,  H01L29/4236 ,  H01L29/452 ,  H01L29/517 ,  H01L29/66522 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7827 ,  H01L29/7836 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78681

Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.

Abstract translation: 描述具有窄带隙半导体源极/漏极区域的晶体管。 晶体管包括形成在形成于硅层上的栅介质层上的栅电极。 一对源极/漏极区域形成在栅电极的相对侧上，其中所述一对源极/漏极区域包括形成在栅电极的相对侧上的硅层中的窄带隙半导体膜。

公开(公告)号：US20090321941A1

公开(公告)日：2009-12-31

申请号：US12215322

申请日：2008-06-25

Applicant: Matthew Metz ,  Gilbert Dewey

Inventor： Matthew Metz ,  Gilbert Dewey

IPC: H01L23/48 ,  H01L21/4763

CPC classification number: H01L21/31645 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/0228 ,  H01L21/3141 ,  H01L21/3162 ,  H01L21/31641 ,  H01L28/40 ,  H01L28/90

Abstract: Embodiments of a phase-stable amorphous high-κ dielectric layer in a device and methods for forming the phase-stable amorphous high-κ dielectric layer in a device are generally described herein. Other embodiments may be described and claimed.

Abstract translation: 装置中相位稳定的非晶高k电介质层的实施方案和装置中形成相稳定非晶高k电介质层的方法一般在此描述。 可以描述和要求保护其他实施例。

公开(公告)号：US07518196B2

公开(公告)日：2009-04-14

申请号：US11064996

申请日：2005-02-23

Applicant: Robert S. Chau ,  Suman Datta ,  Jack Kavalieros ,  Justin K. Brask ,  Mark L. Doczy ,  Matthew Metz

Inventor： Robert S. Chau ,  Suman Datta ,  Jack Kavalieros ,  Justin K. Brask ,  Mark L. Doczy ,  Matthew Metz

IPC: H01L27/088

CPC classification number: H01L29/7848 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/20 ,  H01L29/201 ,  H01L29/207 ,  H01L29/267 ,  H01L29/41783 ,  H01L29/4236 ,  H01L29/452 ,  H01L29/517 ,  H01L29/66522 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7827 ,  H01L29/7836 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78681

Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.

Abstract translation: 描述具有窄带隙半导体源极/漏极区域的晶体管。 晶体管包括形成在形成于硅层上的栅介质层上的栅电极。 一对源极/漏极区域形成在栅电极的相对侧上，其中所述一对源极/漏极区域包括形成在栅电极的相对侧上的硅层中的窄带隙半导体膜。

公开(公告)号：US07425490B2

公开(公告)日：2008-09-16

申请号：US10876400

申请日：2004-06-24

Applicant: Jack Kavalieros ,  Justin K. Brask ,  Mark L. Doczy ,  Uday Shah ,  Matthew Metz ,  Suman Datta ,  Robert S. Chau

Inventor： Jack Kavalieros ,  Justin K. Brask ,  Mark L. Doczy ,  Uday Shah ,  Matthew Metz ,  Suman Datta ,  Robert S. Chau

IPC: H01L21/336

CPC classification number: H01L29/66545 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/66772

Abstract: In a metal gate replacement process, a gate electrode stack may be formed of a dielectric covered by a sacrificial metal layer covered by a polysilicon gate electrode. In subsequent processing of the source/drains, high temperature steps may be utilized. The sacrificial metal layer prevents reactions between the polysilicon gate electrode and the underlying high dielectric constant dielectric. As a result, adverse consequences of the reaction between the polysilicon and the high dielectric constant dielectric material can be reduced.

Abstract translation: 在金属栅极替换工艺中，栅电极堆叠可以由覆盖有多晶硅栅电极的牺牲金属层覆盖的电介质形成。 在源/下水道的后续处理中，可以利用高温步骤。 牺牲金属层防止多晶硅栅极电极和下面的高介电常数电介质之间的反应。 结果，可以降低多晶硅和高介电常数介电材料之间的反应的不良后果。

公开(公告)号：US20070158702A1

公开(公告)日：2007-07-12

申请号：US11322827

申请日：2005-12-30

Applicant: Mark Doczy ,  Matthew Metz ,  Justin Brask ,  Robert Chau ,  Gilbert Dewey

Inventor： Mark Doczy ,  Matthew Metz ,  Justin Brask ,  Robert Chau ,  Gilbert Dewey

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/00

CPC classification number: H01L29/785 ,  H01L29/4908

Abstract: A transistor comprising a semiconductor including a source, a drain, and a channel interposed between the source and the drain; a first dielectric layer having a first thickness, the first dielectric layer being positioned on the channel; a second dielectric layer having a second thickness, the second dielectric layer being positioned on the first dielectric layer; and a gate electrode on the second dielectric layer, wherein the transistor gate is made of a mid-gap metal. A process comprising depositing a first dielectric layer on at least one surface of a semiconductor layer; depositing a second dielectric layer on the first dielectric layer; depositing a layer of mid-gap metal on the second dielectric layer; and patterning and etching the first dielectric layer, the second dielectric layer and the layer of mid-gap metal to create a gate electrode separated from the substrate by a first dielectric and a second dielectric. Other embodiments are disclosed and claimed.

Abstract translation: 一种晶体管，包括：半导体，包括源极，漏极和介于源极和漏极之间的沟道; 具有第一厚度的第一介电层，所述第一介电层位于所述通道上; 具有第二厚度的第二介电层，所述第二介电层位于所述第一介电层上; 以及第二介质层上的栅电极，其中晶体管栅极由中间间隙金属制成。 一种方法，包括在半导体层的至少一个表面上沉积第一介电层; 在所述第一电介质层上沉积第二电介质层; 在所述第二电介质层上沉积中间间隙金属层; 以及对第一电介质层，第二电介质层和中间间隙金属层进行图案化和蚀刻以产生通过第一电介质和第二电介质与衬底分离的栅电极。 公开和要求保护其他实施例。

公开(公告)号：US20070145498A1

公开(公告)日：2007-06-28

申请号：US11320305

申请日：2005-12-27

Applicant: Matthew Metz ,  Mark Doczy ,  Justin Brask ,  Robert Chau

Inventor： Matthew Metz ,  Mark Doczy ,  Justin Brask ,  Robert Chau

IPC: H01L29/94

CPC classification number: H01L29/0847 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/66636

Abstract: Embodiments of the invention provide a device with a metal gate, a high-k gate dielectric layer and reduced oxidation of a substrate beneath the high-k gate dielectric layer. An oxygen-scavenging spacer layer on side walls of the high-k gate dielectric layer and metal gate may reduce such oxidation during high temperature processes.

Abstract translation: 本发明的实施例提供一种具有金属栅极，高k栅极电介质层和在高k栅极电介质层下面的衬底的氧化减少的器件。 在高k栅极电介质层和金属栅极的侧壁上的氧气清除间隔层可以在高温过程中减少这种氧化。

公开(公告)号：US20070138565A1

公开(公告)日：2007-06-21

申请号：US11305452

申请日：2005-12-15

Applicant: Suman Datta ,  Mantu Hudait ,  Mark Doczy ,  Jack Kavalleros ,  Majumdar Amlan ,  Justin Brask ,  Been-Yih Jin ,  Matthew Metz ,  Robert Chau

Inventor： Suman Datta ,  Mantu Hudait ,  Mark Doczy ,  Jack Kavalleros ,  Majumdar Amlan ,  Justin Brask ,  Been-Yih Jin ,  Matthew Metz ,  Robert Chau

IPC: H01L29/94

CPC classification number: H01L29/7784 ,  H01L21/02178 ,  H01L21/02381 ,  H01L21/02546 ,  H01L21/823807 ,  H01L21/823885 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/122 ,  H01L29/15 ,  H01L29/157 ,  H01L29/205 ,  H01L29/41783 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/7783

Abstract: A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate.

Abstract translation: CMOS器件包括具有第一量子阱结构的PMOS晶体管和具有第二量子阱结构的NMOS器件。 PMOS和NMOS晶体管形成在衬底上。

公开(公告)号：US20060186484A1

公开(公告)日：2006-08-24

申请号：US11064996

申请日：2005-02-23

Applicant: Robert Chau ,  Suman Datta ,  Jack Kavalieros ,  Justin Brask ,  Mark Doczy ,  Matthew Metz

Inventor： Robert Chau ,  Suman Datta ,  Jack Kavalieros ,  Justin Brask ,  Mark Doczy ,  Matthew Metz

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7848 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/20 ,  H01L29/201 ,  H01L29/207 ,  H01L29/267 ,  H01L29/41783 ,  H01L29/4236 ,  H01L29/452 ,  H01L29/517 ,  H01L29/66522 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7827 ,  H01L29/7836 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78681

Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.