公开(公告)号：US08537609B2

公开(公告)日：2013-09-17

申请号：US13161129

申请日：2011-06-15

Applicant: Ming-Hsiu Lee ,  Chieh-Fang Chen

Inventor： Ming-Hsiu Lee ,  Chieh-Fang Chen

IPC: G11C11/34

CPC classification number: G11C8/08 ,  G11C8/10 ,  G11C11/005 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0073

Abstract: A memory device is provided. The memory device includes a memory array; a first circuit electrically connected to the memory array, and causing the memory array to be operated in a first mode; and a second circuit electrically connected to the memory array, and causing the memory array to be operated in a second mode.

Abstract translation: 提供存储器件。 存储器件包括存储器阵列; 电连接到存储器阵列的第一电路，并使存储器阵列以第一模式工作; 以及电连接到存储器阵列的第二电路，并且使存储器阵列以第二模式工作。

公开(公告)号：US20130153846A1

公开(公告)日：2013-06-20

申请号：US13330525

申请日：2011-12-19

Applicant: Wei-Chih CHIEN ,  Ming-Hsiu Lee ,  Shih-Hung Chen

Inventor： Wei-Chih CHIEN ,  Ming-Hsiu Lee ,  Shih-Hung Chen

IPC: H01L45/00 ,  H01L21/8239

CPC classification number: H01L27/2409 ,  H01L27/249 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1633

Abstract: A self-aligning stacked memory cell array structure and method for fabricating such structure. The memory cell array includes a stack of memory cells disposed adjacent to opposing sides of a conductive line that is formed within a trench. The memory cells are stacked such that the memory element surface of each memory cell forms a portion of the sidewall of the conductive line. The conductive line is formed within the trench such that electrical contact is made across the entire memory element surface of each memory cell. Such structure and method for making such structure is a self-aligning process that does not require the use of any additional masks.

Abstract translation: 一种自对准堆叠式存储单元阵列结构及其制造方法。 存储单元阵列包括与形成在沟槽内的导电线的相对侧相邻设置的一堆存储单元。 存储单元被堆叠，使得每个存储单元的存储元件表面形成导电线的侧壁的一部分。 导电线形成在沟槽内，使得电接触跨越每个存储单元的整个存储元件表面。 用于制造这种结构的这种结构和方法是不需要使用任何附加掩模的自对准过程。

公开(公告)号：US20130026516A1

公开(公告)日：2013-01-31

申请号：US13223479

申请日：2011-09-01

Applicant: Jih-Fu Wang ,  Chien-Ping Huang ,  Wen-Hao Lee ,  Hsien-Wen Chen ,  Ming-Hsiu Lee

Inventor： Jih-Fu Wang ,  Chien-Ping Huang ,  Wen-Hao Lee ,  Hsien-Wen Chen ,  Ming-Hsiu Lee

IPC: H01L33/60

CPC classification number: H01L33/486 ,  H01L33/62 ,  H01L2224/48091 ,  H01L2933/0033 ,  H01L2924/00014

Abstract: A light-emitting diode (LED) package structure and a packaging method thereof are provided. The packaging method includes: forming first conductive layers on a silicon substrate, and forming a reflection cavity and electrode via holes from a top surface of the silicon substrate; forming a reflection layer on predetermined areas of a surface of the reflection cavity, and forming second conductive layers and metal layers on surfaces of the electrode via holes; and mounting a chip and forming an encapsulant, so as to fabricate the LED package structure. In the present invention, there is no need to perform at least two plating processes for connecting upper and lower conductive layers of the silicon substrate in the electrode via holes, and the problem of poor connection of the conductive layers in the electrode via holes can be avoided, thereby making the fabrication processes simplified and time-effective and also improving the overall production yield.

Abstract translation: 提供一种发光二极管（LED）封装结构及其封装方法。 封装方法包括：在硅衬底上形成第一导电层，并从硅衬底的顶表面形成反射腔和电极通孔; 在所述反射腔的表面的规定区域上形成反射层，在所述电极通孔的表面形成第二导电层和金属层; 并安装芯片并形成密封剂，以制造LED封装结构。 在本发明中，不需要在电极通孔中进行用于连接硅基板的上下导电层的至少两个电镀工艺，并且导电层在电极通孔中的连接不良的问题可以是 避免了，从而使制造工艺简化和时间有效，并且还提高了总产量。

公开(公告)号：US08238149B2

公开(公告)日：2012-08-07

申请号：US12715802

申请日：2010-03-02

Applicant: Yen-Hao Shih ,  Ming-Hsiu Lee ,  Chao-I Wu ,  Hsiang-Lan Lung ,  Chung Hon Lam ,  Roger Cheek ,  Matthew J. Breitwisch ,  Bipin Rajendran

Inventor： Yen-Hao Shih ,  Ming-Hsiu Lee ,  Chao-I Wu ,  Hsiang-Lan Lung ,  Chung Hon Lam ,  Roger Cheek ,  Matthew J. Breitwisch ,  Bipin Rajendran

IPC: G11C11/00

CPC classification number: G11C13/0004 ,  G11C13/004 ,  G11C29/70 ,  G11C2213/79

Abstract: Phase change memory devices and methods for operating described herein are based on the discovery that, following an initial high current operation applied to a phase change memory cell to establish the high resistance reset state, the current-voltage (I-V) behavior of the memory cell under different bias voltages can be used to detect if the memory cell is a defect cell having poor data retention characteristics.

Abstract translation: 相位变化存储器件和这里描述的操作方法基于以下发现：在施加到相变存储器单元以建立高电阻复位状态的初始高电流操作之后，存储器单元的电流 - 电压（IV）行为 可以使用不同的偏置电压来检测存储器单元是否具有差的数据保留特性的缺陷单元。

公开(公告)号：US08203187B2

公开(公告)日：2012-06-19

申请号：US12705158

申请日：2010-02-12

Applicant: Hsiang-Lan Lung ,  Yen-Hao Shih ,  Erh-Kun Lai ,  Ming Hsiu Lee ,  Hang-Ting Lue

Inventor： Hsiang-Lan Lung ,  Yen-Hao Shih ,  Erh-Kun Lai ,  Ming Hsiu Lee ,  Hang-Ting Lue

IPC: H01L29/76

CPC classification number: G11C16/0458 ,  H01L27/0688 ,  H01L27/10 ,  H01L27/11578 ,  H01L27/11582

Abstract: A 3D memory device includes an array of semiconductor body pillars and bit line pillars, dielectric charge trapping structures, and a plurality of levels of word line structures arranged orthogonally to the array of semiconductor body pillars and bit line pillars. The semiconductor body pillars have corresponding bit line pillars on opposing first and second sides, providing source and drain terminals. The semiconductor body pillars have first and second channel surfaces on opposing third and fourth sides. Dielectric charge trapping structures overlie the first and second channel surfaces, providing data storage sites on two sides of each semiconductor body pillar in each level of the 3D array. The device can be operated as a 3D AND-decoded flash memory.

Abstract translation: 3D存储器件包括半导体主体柱和位线柱的阵列，介电电荷俘获结构以及与半导体主体柱和位线柱阵列垂直布置的多个字线结构。 半导体主体柱在相对的第一和第二侧上具有对应的位线柱，提供源极和漏极端子。 半导体主体支柱在相对的第三和第四侧上具有第一和第二通道表面。 电介质电荷捕获结构覆盖在第一和第二通道表面上，在3D阵列的每个级别中的每个半导体主体支柱的两侧提供数据存储位置。 该设备可以作为3D和解码的闪存操作。

公开(公告)号：US08077506B2

公开(公告)日：2011-12-13

申请号：US12969526

申请日：2010-12-15

Applicant: Ming-Hsiu Lee ,  Yi-Chou Chen

Inventor： Ming-Hsiu Lee ,  Yi-Chou Chen

IPC: G11C11/00

CPC classification number: G11C13/0069 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2013/0092

Abstract: A method of programming a phase change device includes selecting a desired threshold voltage (Vth) and applying a programming pulse to a phase change material in the phase change device. The applying of the programming pulse includes applying a quantity of energy to the phase change material to drive at least a portion of this material above a melting energy level. A portion of the energy applied to the phase change material is allowed to dissipate below the melting energy level. The shape of the energy dissipation from the phase change material is controlled until the energy applied to the phase change material is less than a quenched energy level, to cause the phase change device to have the desired Vth. A remaining portion of the energy applied to the phase change material is allowed to dissipate to an environmental level.

公开(公告)号：US20110286283A1

公开(公告)日：2011-11-24

申请号：US12785291

申请日：2010-05-21

Applicant: HSIANG-LAN LUNG ,  Hang-Ting Lue ,  Yen-Hao Shih ,  Erh-Kun Lai ,  Ming Hsiu Lee ,  Tien-Yen Wang

Inventor： HSIANG-LAN LUNG ,  Hang-Ting Lue ,  Yen-Hao Shih ,  Erh-Kun Lai ,  Ming Hsiu Lee ,  Tien-Yen Wang

IPC: G11C16/04 ,  H01L21/336

CPC classification number: H01L27/11578 ,  G11C16/0483 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

Abstract: A 3D memory device is described which includes bottom and top memory cubes having respective arrays of vertical NAND string structures. A common source plane comprising a layer of conductive material is between the top and bottom memory cubes. The source plane is supplied a bias voltage such as ground, and is selectively coupled to an end of the vertical NAND string structures of the bottom and top memory cubes. Memory cells in a particular memory cube are read using current through the particular vertical NAND string between the source plane and a corresponding bit line coupled to another end of the particular vertical NAND string.

Abstract translation: 描述了一种3D存储器件，其包括具有垂直NAND串结构的相应阵列的底部和顶部存储器立方体。 包括导电材料层的共同源平面位于顶部和底部存储立方体之间。 源平面被提供诸如地的偏置电压，并且选择性地耦合到底部和顶部存储立方体的垂直NAND串结构的一端。 通过源平面与耦合到特定垂直NAND串的另一端的对应位线之间的特定垂直NAND串的电流来读取特定存储器立方体中的存储单元。

公开(公告)号：US08064247B2

公开(公告)日：2011-11-22

申请号：US12488795

申请日：2009-06-22

Applicant: Ming-Hsiu Lee ,  Chieh-Fang Chen ,  Yen-Hao Shih ,  Yu Zhu

Inventor： Ming-Hsiu Lee ,  Chieh-Fang Chen ,  Yen-Hao Shih ,  Yu Zhu

IPC: G11C11/00

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C2013/0071 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/33 ,  G11C2213/79 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1625

Abstract: Memory devices described herein are programmed and erased by physical segregation of an electrically insulating layer out of a memory material to establish a high resistance state, and by re-absorption of at least a portion of the electrically insulating layer into the memory material to establish a low resistance state. The physical mechanism of programming and erasing includes movement of structure vacancies to form voids, and/or segregation of doping material and bulk material, to create the electrically insulating layer consisting of voids and/or dielectric doping material along an inter-electrode current path between electrodes.

Abstract translation: 通过将电绝缘层从存储材料中物理分离出来以建立高电阻状态，并且通过将电绝缘层的至少一部分再吸收到存储材料中以建立 低电阻状态。 编程和擦除的物理机制包括结构空位的移动以形成空隙，和/或掺杂材料和体材料的偏析，以产生由空隙和/或介电掺杂材料构成的电绝缘层，沿着电极间电流通路 电极。

公开(公告)号：US07944740B2

公开(公告)日：2011-05-17

申请号：US12564904

申请日：2009-09-22

Applicant: Chung H. Lam ,  Ming-Hsiu Lee ,  Thomas Nirschi ,  Bipin Rajendran

Inventor： Chung H. Lam ,  Ming-Hsiu Lee ,  Thomas Nirschi ,  Bipin Rajendran

IPC: G11C11/00

CPC classification number: G11C13/0004 ,  G11C11/5678 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2013/0092

Abstract: A phase change memory device and a method for programming the same. The method includes determining a characterized lowest SET current and corresponding SET resistance for the phase change memory device. The method includes determining a characterized RESET current slope for the phase change memory device. The method also includes calculating a first current amplitude for a RESET pulse based on the characterized lowest SET current and the characterized RESET current slope. The method includes applying the RESET pulse to a target memory cell in the phase change memory device and measuring the resistance of the target memory cell. If the measured resistance is substantially less than a target resistance, the method further includes applying one or more additional RESET pulses. In one embodiment of the invention, the one or more additional RESET pulses have current amplitudes greater than a previously applied RESET pulse.

Abstract translation: 相变存储器件及其编程方法。 该方法包括确定用于相变存储器件的特征最低的SET电流和相应的SET电阻。 该方法包括确定用于相变存储器件的特征化的RESET电流斜率。 该方法还包括基于所表征的最低SET电流和表征的RESET电流斜率来计算RESET脉冲的第一电流幅度。 该方法包括将RESET脉冲施加到相变存储器件中的目标存储单元并测量目标存储单元的电阻。 如果所测量的电阻远小于目标电阻，该方法还包括应用一个或多个附加的RESET脉冲。 在本发明的一个实施例中，一个或多个附加的RESET脉冲的电流幅度大于先前施加的RESET脉冲。

公开(公告)号：US07869270B2

公开(公告)日：2011-01-11

申请号：US12345384

申请日：2008-12-29

Applicant: Ming-Hsiu Lee

Inventor： Ming-Hsiu Lee

IPC: G11C11/00

CPC classification number: G11C13/0038 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/79

Abstract: Memory devices and methods for operating such devices are described herein. A method is described herein for operating a memory cell comprising phase change material and programmable to a plurality of resistance states including a high resistance state and a lower resistance state. The method comprises applying a first bias arrangement to the memory cell to establish the lower resistance state, the first bias arrangement comprising a first voltage pulse. The method further comprises determining whether the memory cell is in the lower resistance state, and if the memory cell is not in the lower resistance state then applying a second bias arrangement to the memory cell. The second bias arrangement comprises a second voltage pulse having a pulse height greater than that of the first voltage pulse.

Abstract translation: 这里描述了用于操作这样的设备的存储器件和方法。 本文描述了一种用于操作包括相变材料并且可编程为包括高电阻状态和较低电阻状态的多个电阻状态的存储单元的方法。 该方法包括将第一偏置装置施加到存储器单元以建立较低电阻状态，第一偏置装置包括第一电压脉冲。 该方法还包括确定存储器单元是处于较低电阻状态，以及如果存储单元不处于较低电阻状态，则向存储单元施加第二偏置布置。 第二偏置装置包括具有大于第一电压脉冲的脉冲高度的第二电压脉冲。