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245 条记录 (耗时 0.024 秒)

    NONVOLATILE SEMICONDUCTOR MEMORY AND PROCESS OF PRODUCING THE SAME
    95.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY AND PROCESS OF PRODUCING THE SAME 有权
    非易失性半导体存储器及其制造方法

    公开(公告)号：US20110092033A1

    公开(公告)日：2011-04-21

    申请号：US12974873

    申请日：2010-12-21

    申请人： Fumitaka Arai ,  Riichiro Shirota

    发明人： Fumitaka Arai ,  Riichiro Shirota

    IPC分类号： H01L21/71

    CPC分类号： H01L29/792 ,  G11C16/0483 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L29/7926

    摘要： A nonvolatile semiconductor memory of an aspect of the present invention comprises a semiconductor substrate, a pillar-shaped semiconductor layer extending in the vertical direction with respect to the surface of the semiconductor substrate, a plurality of memory cells arranged in the vertical direction on the side surface of the semiconductor layer and having a charge storage layer and a control gate electrode, a first select gate transistor arranged on the semiconductor layer at an end of the memory cells on the side of the semiconductor substrate, and a second select gate transistor arranged on the semiconductor layer on the other end of the memory cells opposite to the side of the semiconductor substrate, wherein the first select gate transistor includes a diffusion layer in the semiconductor substrate and is electrically connected to the pillar-shaped semiconductor layer by way of the diffusion layer that serves as the drain region.

    摘要翻译： 本发明的一个方面的非易失性半导体存储器包括半导体衬底，相对于半导体衬底的表面在垂直方向上延伸的柱状半导体层，沿着垂直方向排列的多个存储单元 具有电荷存储层和控制栅电极的第一选择栅晶体管，布置在半导体衬底侧的存储单元的端部的半导体层上的第一选择栅极晶体管和布置在半导体层上的第二选择栅晶体管 存储单元的与半导体衬底侧相对的另一端的半导体层，其中第一选择栅晶体管包括在半导体衬底中的扩散层，并通过扩散电连接到柱状半导体层 作为漏极区域的层。

    Nonvolatile Semiconductor Memory Device
    96.
    发明申请
    Nonvolatile Semiconductor Memory Device 有权
    非易失性半导体存储器件

    公开(公告)号：US20100226173A1

    公开(公告)日：2010-09-09

    申请号：US12781396

    申请日：2010-05-17

    申请人： Tomoharu Tanaka ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Riichiro Shirota ,  Fumitaka Arai ,  Susumu Fujimura

    发明人： Tomoharu Tanaka ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Riichiro Shirota ,  Fumitaka Arai ,  Susumu Fujimura

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/345 ,  G11C16/3454 ,  G11C16/3459 ,  G11C16/3463 ,  G11C2211/5621

    摘要： A NAND cell unit includes memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in an erase operation, is applied to all memory cells, thereby setting all memory cells out of an over-erased state. Thereafter, a program voltage of 20V is applied to the control gate of a selected memory cell, 0V is applied to the control gates of the two memory cells provided adjacent to the selected memory cell, and 11V is applied to the control gates of the remaining memory cells. Data is thereby programmed into the selected memory cell. The time for which the program voltage is applied to the selected memory cell is adjusted in accordance with the data to be programmed into the selected memory cell. Hence, data “0” can be correctly programmed into the selected memory cell, multi-value data can be read from any selected memory cell at high speed.

    摘要翻译： NAND单元单元包括串联连接的存储单元。 对所有存储单元进行擦除操作。 然后，将与擦除操作中施加的擦除电压极性相反的软编程电压施加到所有存储单元，从而将所有存储单元设置为过擦除状态。 此后，将20V的编程电压施加到所选择的存储单元的控制栅极，将0V施加到与所选存储单元相邻设置的两个存储单元的控制栅极，并且将11V施加到其余的控制栅极 记忆细胞 因此数据被编程到所选择的存储单元中。 根据要编程到所选择的存储单元中的数据来调整对所选存储单元施加编程电压的时间。 因此，可以将数据“0”正确地编程到所选择的存储单元中，可以从任何选择的存储单元高速读取多值数据。

    Semiconductor memory device including pillar-shaped semiconductor layers and a method of fabricating the same
    97.
    发明授权
    Semiconductor memory device including pillar-shaped semiconductor layers and a method of fabricating the same 失效
    包括柱状半导体层的半导体存储器件及其制造方法

    公开(公告)号：US07696559B2

    公开(公告)日：2010-04-13

    申请号：US11616522

    申请日：2006-12-27

    申请人： Fumitaka Arai ,  Riichiro Shirota ,  Makoto Mizukami

    发明人： Fumitaka Arai ,  Riichiro Shirota ,  Makoto Mizukami

    IPC分类号： H01L27/115

    CPC分类号： H01L29/792 ,  G11C16/0483 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/7926

    摘要： A semiconductor memory device includes: a semiconductor substrate, on which an impurity diffusion layer is formed in a cell array area; a gate wiring stack body formed on the cell array area, in which multiple gate wirings are stacked and separated from each other with insulating films; a gate insulating film formed on the side surface of the gate wiring stack body, in which an insulating charge storage layer is contained, pillar-shaped semiconductor layers arranged along the gate wiring stack body, one side surfaces of which are opposed to the gate wiring stack body via the gate insulating film, each pillar-shaped semiconductor layer having the same conductivity type as the impurity diffusion layer; and data lines formed to be in contact with the upper surfaces of the pillar-shaped semiconductor layers and intersect the gate wirings.

    摘要翻译： 半导体存储器件包括：在单元阵列区域中形成有杂质扩散层的半导体衬底; 形成在电池阵列区域上的栅极布线堆叠体，其中多个栅极布线彼此堆叠并且用绝缘膜分离; 形成在栅极布线堆叠体的侧表面上的栅极绝缘膜，其中包含绝缘电荷存储层，沿着栅极布线堆叠体布置的柱状半导体层，其一个侧表面与栅极布线相对 堆叠体经由栅极绝缘膜，每个柱状半导体层具有与杂质扩散层相同的导电类型; 以及形成为与柱状半导体层的上表面接触并与栅极布线相交的数据线。

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD
    100.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD 有权
    半导体器件和制造方法

    公开(公告)号：US20070187749A1

    公开(公告)日：2007-08-16

    申请号：US11733488

    申请日：2007-04-10

    申请人： Kikuko Sugimae ,  Hiroyuki Kutsukake ,  Masayuki Ichige ,  Michiharu Matsui ,  Yuji Takeuchi ,  Riichiro Shirota

    发明人： Kikuko Sugimae ,  Hiroyuki Kutsukake ,  Masayuki Ichige ,  Michiharu Matsui ,  Yuji Takeuchi ,  Riichiro Shirota

    IPC分类号： H01L29/788

    CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529

    摘要： A semiconductor device comprises a memory cell array portion and peripheral circuit portion, wherein a first insulation film including elements as main components other than nitrogen fills between the memory cell gate electrodes of the memory cell array portion, the first insulation film is formed as a liner on a sidewall of a peripheral gate electrode of the peripheral circuit portion simultaneously with the memory cell portion, and a second insulation film including nitrogen as the main component is formed on the sidewall of the peripheral gate electrode via the first insulation film, thus enabling not only the formation of the memory cell portion having high reliability, but also the formation of a peripheral circuit with good efficiency, simultaneously, and avoiding gate offset of a peripheral gate.

    摘要翻译： 半导体器件包括存储单元阵列部分和外围电路部分，其中包括作为除氮之外的主要成分的元素的第一绝缘膜填充在存储单元阵列部分的存储单元栅电极之间，第一绝缘膜形成为衬垫 在周边电路部分的外围栅电极的侧壁上与存储单元部分同时，并且通过第一绝缘膜在外围栅电极的侧壁上形成包括氮作为主要成分的第二绝缘膜，从而不能 仅形成具有高可靠性的存储单元部分，而且形成具有良好效率的周边电路，同时避免了外围栅极的栅极偏移。