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    On-chip memory cell and method of manufacturing same
    91.
    发明申请
    On-chip memory cell and method of manufacturing same 审中-公开
    片上存储单元及其制造方法

    公开(公告)号：US20080237678A1

    公开(公告)日：2008-10-02

    申请号：US11729192

    申请日：2007-03-27

    Applicant: Suman Datta ,  Jack T. Kavalieros ,  Brian S. Doyle ,  Dinesh Somasekhar ,  Ali Keshavarzi

    Inventor： Suman Datta ,  Jack T. Kavalieros ,  Brian S. Doyle ,  Dinesh Somasekhar ,  Ali Keshavarzi

    IPC: H01L27/108 ,  H01L21/336

    CPC classification number: H01L27/10873 ,  H01L27/10826 ,  H01L29/785

    Abstract: An on-chip memory cell comprises a tri-gate access transistor (145) and a tri-gate capacitor (155). The on-chip memory cell may be an embedded DRAM on a three-dimensional tri-gate transistor and capacitor structures which is fully compatible with existing tri-gate logic transistor fabrication process. Embodiments of the invention use the high fin aspect ratio and inherently superior surface area of the tri-gate transistors to replace the “trench” capacitor in a commodity DRAM with an inversion mode tri-gate capacitor. The tall sidewalls of the tri-gate transistor provide large enough surface area to provide storage capacitance in a small cell area.

    Abstract translation: 片上存储单元包括三栅极存取晶体管（145）和三栅极电容器（155）。 片上存储器单元可以是三维三栅晶体管上的嵌入式DRAM和与现有三栅逻辑晶体管制造工艺完全兼容的电容器结构。 本发明的实施例使用三栅极晶体管的高翅片长宽比和固有优越的表面积来替代具有反向模式三栅极电容器的商品DRAM中的“沟槽”电容器。 三栅极晶体管的高侧壁提供足够大的表面积，以在小单元区域中提供存储电容。

    Methods for uniform doping of non-planar transistor structures
    96.
    发明申请
    Methods for uniform doping of non-planar transistor structures 有权
    均匀掺杂非平面晶体管结构的方法

    公开(公告)号：US20080085580A1

    公开(公告)日：2008-04-10

    申请号：US11529963

    申请日：2006-09-29

    Applicant: Brian Doyle ,  Robert Chau ,  Suman Datta ,  Jack Kavalieros

    Inventor： Brian Doyle ,  Robert Chau ,  Suman Datta ,  Jack Kavalieros

    IPC: H01L21/8238 ,  H01L29/94

    CPC classification number: H01L21/823437 ,  H01L21/2236 ,  H01L21/26586 ,  H01L29/66803 ,  H01L29/7851

    Abstract: Methods for uniformly tip doping a silicon body of a non-planar transistor and devices and systems formed by such methods. In one embodiment, a method can include vertical tip ion implantation of a silicon body with at least three surfaces on a substrate followed by conformal deposition of a dielectric material. The dielectric material can be selectively etched to expose a top surface of the silicon body followed by selective re-oxidation of the top surface for form a mask. The remaining dielectric material can be removed followed by angled ion implantation of at least two sidewalls of the silicon body. The mask can be removed resulting in a silicon body with uniform doping.

    Abstract translation: 用于均匀尖端掺杂非平面晶体管的硅体的方法以及通过这种方法形成的器件和系统。 在一个实施例中，一种方法可以包括在衬底上具有至少三个表面的硅体的垂直尖端离子注入，随后是电介质材料的共形沉积。 可以选择性地蚀刻介电材料以暴露硅体的顶表面，随后选择性地再次氧化顶表面以形成掩模。 可以除去剩余的电介质材料，然后对硅体的至少两个侧壁进行成角度的离子注入。 可以去除掩模，从而产生均匀掺杂的硅体。

    PINNING LAYER FOR LOW RESISTIVITY N-TYPE SOURCE DRAIN OHMIC CONTACTS
    98.
    发明申请
    PINNING LAYER FOR LOW RESISTIVITY N-TYPE SOURCE DRAIN OHMIC CONTACTS 有权
    密封层用于低电阻N型源漏管OHMIC接触

    公开(公告)号：US20080017891A1

    公开(公告)日：2008-01-24

    申请号：US11480667

    申请日：2006-06-30

    Applicant: Suman Datta ,  Jack T. Kavalieros ,  Robert S. Chau ,  Mark L. Doczy

    Inventor： Suman Datta ,  Jack T. Kavalieros ,  Robert S. Chau ,  Mark L. Doczy

    IPC: H01L29/76 ,  H01L29/745

    CPC classification number: H01L29/0847 ,  H01L21/28525 ,  H01L29/7833

    Abstract: A system or apparatus including an N-type transistor structure including a gate electrode formed on a substrate and source and drain regions formed in the substrate; a contact to the source region; and a pinning layer disposed between the source region and the first contact and defining an interface between the pinning layer and the source region, wherein the pinning layer has donor-type surface states in a conduction band. A method including forming a transistor structure including a gate electrode on a substrate and source and drain regions formed in the substrate; depositing a pinning layer having donor-type surface states on the source and drain regions such that an interface is defined between the pinning layer and the respective one of the source and drain regions; and forming a first contact to the source region and a second contact to the drain region.

    Abstract translation: 一种包括N型晶体管结构的系统或装置，包括形成在衬底上的栅电极和形成在衬底中的源区和漏区; 与源区的联系; 以及钉扎层，其设置在所述源区域和所述第一触点之间并且限定所述钉扎层和所述源区域之间的界面，其中所述钉扎层在导带中具有施主型表面状态。 一种包括在衬底上形成包括栅电极的晶体管结构和形成在衬底中的源极和漏极区的方法; 在源极和漏极区域上沉积具有施主型表面状态的钉扎层，使得在钉扎层与源极和漏极区域中的相应一个之间界定界面; 以及向所述源极区域形成第一接触和向所述漏极区域形成第二接触。

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