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    METHODOLOGY OF IMPROVING THE MANUFACTURABILITY OF LASER ANNEAL
    91.
    发明申请
    METHODOLOGY OF IMPROVING THE MANUFACTURABILITY OF LASER ANNEAL 有权
    改善激光天线的制造方法

    公开(公告)号：US20080272097A1

    公开(公告)日：2008-11-06

    申请号：US11743440

    申请日：2007-05-02

    申请人： Haowen Bu ,  Amitabh Jain

    发明人： Haowen Bu ,  Amitabh Jain

    IPC分类号： B23K26/00

    CPC分类号： C21D1/26 ,  B23K26/0853 ,  B23K2101/40 ,  C21D9/50

    摘要： A method of laser annealing a workpiece for reduction of warpage, slip defects and breakage, the method comprising (a) moving a workpiece through a laser beam in a x-axis first direction, (b) moving the workpiece in a y-axis second direction, (c) moving the workpiece through a laser beam in a minus x-axis first direction and repeating (a)-(c) until the workpiece is fully annealed in two successive laser annealing iterations.

    摘要翻译： 一种对工件进行激光退火以减少翘曲，滑动缺陷和断裂的方法，所述方法包括：（a）沿x轴第一方向移动通过激光束的工件，（b）在y轴第二方向上移动工件 方向，（c）通过激光束沿负x轴第一方向移动工件，并重复（a） - （c），直到工件在两次连续的激光退火迭代中完全退火。

    Method of Manufacturing a Semiconductor Device Having Reduced N/P or P/N Junction Crystal Disorder
    92.
    发明申请
    Method of Manufacturing a Semiconductor Device Having Reduced N/P or P/N Junction Crystal Disorder 有权
    制造具有减少的N / P或P / N结晶体障碍的半导体器件的方法

    公开(公告)号：US20080145992A1

    公开(公告)日：2008-06-19

    申请号：US11951448

    申请日：2007-12-06

    申请人： Amitabh Jain

    发明人： Amitabh Jain

    IPC分类号： H01L21/336

    CPC分类号： H01L21/26506 ,  H01L21/26513 ,  H01L21/26566 ,  H01L21/2658 ,  H01L21/268 ,  H01L29/6659

    摘要： One aspect provides a method of manufacturing a semiconductor device having reduced N/P or P/N junction crystal disorder. In one aspect, this improvement is achieved by forming gate electrodes over a semiconductor substrate, amorphizing the semiconductor substrate that creates amorphous regions adjacent the gate electrodes to a depth in the semiconductor substrate. Source/drains are formed adjacent the gate electrodes by placing conductive dopants in the semiconductor substrate, wherein displaced substrate atoms and the conductive dopants are contained within the depth of the amorphous regions. The semiconductor substrate is annealed to re-crystallize the amorphous regions subsequent to forming the source/drains.

    摘要翻译： 一方面提供一种制造具有降低的N / P或P / N结晶体紊乱的半导体器件的方法。 在一个方面，这种改进通过在半导体衬底上形成栅电极来实现，使半导体衬底非晶化，该半导体衬底产生与栅电极相邻的非晶区到达半导体衬底的深度。 源极/漏极通过在半导体衬底中放置导电掺杂剂而形成在栅极附近，其中位移的衬底原子和导电掺杂剂包含在非晶区域的深度内。 在形成源极/漏极之后，半导体衬底被退火以使无定形区域再结晶。

    Method for Preparing a Source Material for Ion Implantation
    94.
    发明申请
    Method for Preparing a Source Material for Ion Implantation 有权
    离子植入材料的制备方法

    公开(公告)号：US20070178651A1

    公开(公告)日：2007-08-02

    申请号：US11697790

    申请日：2007-04-09

    申请人： Amitabh Jain

    发明人： Amitabh Jain

    IPC分类号： H01L21/336

    CPC分类号： H01J37/08 ,  H01J2237/31701 ,  H01L21/26513 ,  H01L21/823418 ,  H01L29/6659 ,  Y10S252/95

    摘要： The present invention provides, for use in a semiconductor manufacturing process, a method (100) of preparing an ion-implantation source material. The method includes providing (110) a deliquescent ion implantation source material and mixing (110) the deliquescent ion implantation source material with an organic liquid to form a paste.

    摘要翻译： 为了在半导体制造工艺中使用本发明，提供了制备离子注入源材料的方法（100）。 该方法包括提供（110）潮解离子注入源材料，并将潮解离子注入源材料与有机液体混合（110）以形成糊状物。

    Source/drain extensions having highly activated and extremely abrupt junctions
    95.
    发明授权
    Source/drain extensions having highly activated and extremely abrupt junctions 有权
    源/漏扩展具有高度激活和极其突点

    公开(公告)号：US07247535B2

    公开(公告)日：2007-07-24

    申请号：US10955270

    申请日：2004-09-30

    申请人： Amitabh Jain

    发明人： Amitabh Jain

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/66636 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

    摘要： A method for making a transistor within a semiconductor wafer. The method may include etching a recess at source/drain extension locations 90 and depositing SiGe within the recess to form SiGe source/drain extensions 90. Dopants are implanted into the SiGe source/drain extensions 90 and the semiconductor wafer 10 is annealed. Also, a transistor source/drain region 80, 90 having a SiGe source/drain extension 90 that contains evenly distributed dopants, is highly doped, and has highly abrupt edges.

    摘要翻译： 一种在半导体晶片内制造晶体管的方法。 该方法可以包括在源极/漏极扩展位置90处蚀刻凹陷并在凹槽内沉积SiGe以形成SiGe源极/漏极延伸部90。 将掺杂剂注入到SiGe源极/漏极延伸部分90中，并且半导体晶片10被退火。 此外，具有含有均匀分布的掺杂剂的SiGe源极/漏极延伸部90的晶体管源极/漏极区域80,90是高度掺杂的，并且具有高度突变的边缘。

    Complementary junction-narrowing implants for ultra-shallow junctions
    98.
    发明申请
    Complementary junction-narrowing implants for ultra-shallow junctions 有权
    用于超浅交叉点的互补连接收缩植入物

    公开(公告)号：US20050042848A1

    公开(公告)日：2005-02-24

    申请号：US10942607

    申请日：2004-09-15

    申请人： Amitabh Jain ,  Stephanie Butler

    发明人： Amitabh Jain ,  Stephanie Butler

    IPC分类号： H01L21/265 ,  H01L21/324 ,  H01L21/336 ,  H01L29/10 ,  H01L29/78 ,  H01L21/425

    CPC分类号： H01L29/6659 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/324 ,  H01L29/1083 ,  H01L29/7833

    摘要： Methods are disclosed for forming ultra shallow junctions in semiconductor substrates using multiple ion implantation steps. The ion implantation steps include implantation of at least one electronically-active dopant as well as the implantation of at least two species effective at limiting junction broadening by channeling during dopant implantation and/or by thermal diffusion. Following dopant implantation, the electronically-active dopant is activated by thermal processing.

    摘要翻译： 公开了使用多个离子注入步骤在半导体衬底中形成超浅结的方法。 离子注入步骤包括植入至少一种电子活性掺杂剂以及通过在掺杂剂注入期间通过沟槽化和/或通过热扩散来有效地限制结扩展的至少两种物质的注入。 在掺杂剂注入之后，电子活性掺杂剂通过热处理而被激活。

    Use of indium to define work function of p-type doped polysilicon
    99.
    发明授权
    Use of indium to define work function of p-type doped polysilicon 有权

    公开(公告)号：US06803611B2

    公开(公告)日：2004-10-12

    申请号：US10336563

    申请日：2003-01-03

    申请人： Antonio Luis Pacheco Rotondaro ,  James J. Chambers ,  Amitabh Jain

    发明人： Antonio Luis Pacheco Rotondaro ,  James J. Chambers ,  Amitabh Jain

    IPC分类号： H01L2710

    CPC分类号： H01L29/4925 ,  H01L21/28035 ,  H01L21/2807

    摘要： The present invention pertains to formation of a PMOS transistor wherein a layer of silicon or SiGe inhibits p-type dopant from entering into an underlying gate dielectric layer. The p-type dopant can be added to a gate electrode material that overlies the silicon or SiGe layer and can diffuse down toward the silicon or SiGe layer. The layer of silicon or SiGe may be formed to a thickness of about 5 to 120 nanometers and doped with a dopant, such as indium (In), for example, to deter the p-type dopant from passing through the silicon or SiGe layer. The dopant may have a peak concentration within the layer of silicon or SiGe near the interface of the silicon or SiGe layer with the underlying layer of gate dielectric material. Allowing the gate electrode to be doped with the p-type dopant (e.g., boron) facilitates forming the transistor with an associated work function having a desired value (e.g., coincident with a Fermi level of about 4.8 to about 5.6 electron volts).