公开(公告)号：US11446661B2

公开(公告)日：2022-09-20

申请号：US16643464

申请日：2019-03-11

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xiaochen Ma ,  Guangcai Yuan ,  Ce Ning ,  Zhengliang Li

IPC: B01L3/00 ,  G01N35/10

Abstract: A microfluidic channel and a preparation method and an operation method thereof. The microfluidic channel includes: a channel structure, including a channel for a liquid sample to flow through and a channel wall surrounding the channel. The channel wall includes an electrolyte layer made of an electrolyte material; and a control electrode layer, at a side of the electrolyte layer away from the channel. The control electrode layer overlaps with the electrolyte layer with respect to the channel.

公开(公告)号：US11362114B2

公开(公告)日：2022-06-14

申请号：US16765216

申请日：2019-12-06

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Wei Yang ,  Guangcai Yuan ,  Ce Ning ,  Xinhong Lu ,  Tianmin Zhou ,  Xin Yang

IPC: H01L27/12

Abstract: A method of manufacturing an array substrate includes: forming a first semiconductor pattern and a first insulating layer group sequentially on a base substrate; forming a second semiconductor pattern and a second insulating layer group sequentially on the first insulating layer group; forming two first via holes in the first insulating layer group and the second insulating layer group to expose the first semiconductor pattern, annealing the exposed first semiconductor pattern and then removing an oxide layer on a surface of the first semiconductor pattern; forming connecting wires in the first via holes; forming second via holes in the second insulating layer group to expose the second semiconductor pattern, and forming a first source electrode and a first drain electrode in the second via holes such that the first source electrode or the first drain electrode covers and is connected to one of the connecting wires.

公开(公告)号：US11257954B2

公开(公告)日：2022-02-22

申请号：US16959179

申请日：2019-11-19

Applicant: BOE Technology Group Co., Ltd.

Inventor： Xiaochen Ma ,  Guangcai Yuan ,  Ce Ning ,  Xin Gu ,  Hehe Hu

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/417

Abstract: Provided are a thin film transistor including: a base cushion layer having a recessed portion, base insulating layer, source-drain layer and active layer. The base insulating layer is located on a side of the base cushion layer where the recessed portion is located, and has a first and second partition walls that are spaced apart, and an orthographic projection region of a gap region between the first and second partition walls onto the base cushion layer is located at a region where the recessed portion is located; and both orthographic projection regions of the first and second partition walls onto the base cushion layer partially overlap with the recessed portion region; and both the source-drain layer and the active layer are located on the side of the base insulating layer away from the base cushion layer.

公开(公告)号：US11189679B2

公开(公告)日：2021-11-30

申请号：US16711972

申请日：2019-12-12

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Jing Feng ,  Dongsheng Yin ,  Ce Ning ,  Jiushi Wang

IPC: H01L29/08 ,  H01L27/32

Abstract: An array substrate includes a base substrate and a plurality of pixel units disposed on a base substrate, and at least one pixel unit includes a plurality of thin film transistors, a first electrode, and a second electrode. The plurality of thin film transistors include at least one first thin film transistor including a first active pattern, a first gate, a first source and a first drain. The first electrode is disposed in a same layer as the first active pattern, the first electrode is coupled to the first drain, and the second electrode is disposed in a same layer as the first gate. Orthographic projections of any two in a group consisting of the first electrode, the second electrode, and the first drain on the base substrate have an overlapping region.

公开(公告)号：US20210359063A1

公开(公告)日：2021-11-18

申请号：US16330719

申请日：2018-09-11

Applicant: BOE Technology Group Co., Ltd.

Inventor： Xinhong Lu ,  Ke Wang ,  Hehe Hu ,  Ce Ning ,  Wei Yang

IPC: H01L27/32 ,  H01L29/786

Abstract: An array substrate includes a base substrate; a first thin film transistor on the base substrate and including a first active layer, a first gate electrode, a first source electrode and a first drain electrode; a second thin film transistor on the base substrate and including a second active layer, a second gate electrode, a second source electrode and a second drain electrode; a first gate insulating layer between the first active layer and the first gate electrode; and a second gate insulating layer between the second active layer and the second gate electrode, the second gate insulating layer being different from the first gate insulating layer. The first source electrode, the first drain electrode, and the second gate electrode are in a same layer. The first source electrode and the first drain electrode are on a side of the second gate insulating layer distal to the base substrate.

公开(公告)号：US20210331168A1

公开(公告)日：2021-10-28

申请号：US16605776

申请日：2019-05-06

Applicant: BOE Technology Group Co., Ltd.

Inventor： Xiaochen Ma ,  Guangcai Yuan ,  Ce Ning ,  Xin Gu ,  Hehe Hu

IPC: B01L3/00 ,  G01N27/12

Abstract: A biosensor apparatus is provided. The biosensor apparatus includes a base substrate; a first fluid channel layer on the base substrate and having a first fluid channel passing therethrough; a foundation layer on a side of the first fluid channel layer away from the base substrate, a foundation layer throughhole extending through the foundation layer to connect to the first fluid channel; and a micropore layer on a side of the foundation layer away from the base substrate, a micropore extending through the micropore layer to connect to the first fluid channel through the foundation layer throughhole. The micropore layer extends into the foundation layer throughhole and at least partially covers an inner wall of the foundation layer throughhole.

公开(公告)号：US10332987B2

公开(公告)日：2019-06-25

申请号：US15554446

申请日：2017-01-20

Applicant: BOE Technology Group Co., Ltd.

Inventor： Ce Ning ,  Wei Yang ,  Hehe Hu

IPC: H01L21/00 ,  H01L29/66 ,  H01L21/77 ,  H01L21/426 ,  H01L21/44 ,  H01L21/4757 ,  H01L21/4763 ,  H01L29/786 ,  H01L21/465 ,  H01L21/425

Abstract: A thin film transistor, a manufacturing method for an array substrate, the array substrate, and a display device are provided. The manufacturing method for a thin film transistor includes: forming a semiconductor layer; performing a modification treatment on a surface layer of a region of the semiconductor layer, so that the region of the semiconductor layer has a portion in a first direction perpendicular to the semiconductor layer formed as an etching blocking layer, portions of the semiconductor layer on both sides of the etching blocking layer in a second direction parallel to a surface of the semiconductor layer remaining unmodified; and forming a source electrode and a drain electrode on the semiconductor layer, the source electrode and the drain electrode being formed on both sides of a center line of the region perpendicular to the second direction, and spaced from each other in the second direction.

公开(公告)号：US20180212059A1

公开(公告)日：2018-07-26

申请号：US15744954

申请日：2017-03-06

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Ce Ning ,  Wei Yang

IPC: H01L29/786 ,  H01L21/02 ,  H01L21/027 ,  H01L21/425 ,  H01L21/4763 ,  H01L27/12 ,  H01L29/24 ,  H01L29/45 ,  H01L29/66

CPC classification number: H01L29/7869 ,  G02F1/1362 ,  G02F1/1368 ,  H01L21/02565 ,  H01L21/0273 ,  H01L21/425 ,  H01L21/47635 ,  H01L27/1225 ,  H01L27/1288 ,  H01L29/24 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/786

Abstract: The present application discloses a thin film transistor including a base substrate; an active layer on the base substrate having a channel region, a source electrode contact region, and a drain electrode contact region; an etch stop layer on a side of the channel region distal to the base substrate covering the channel region; a source electrode on a side of the source electrode contact region distal to the base substrate; and a drain electrode on a side of the drain electrode contact region distal to the base substrate. A thickness of the active layer in the source electrode contact region and the drain electrode contact region is substantially the same as a combined thickness of the active layer in the channel region and the etch stop layer.

公开(公告)号：US09698165B2

公开(公告)日：2017-07-04

申请号：US14359645

申请日：2013-10-18

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Ce Ning ,  Tao Gao

IPC: H01L27/12 ,  H01L29/45 ,  H01L29/786

CPC classification number: H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/45 ,  H01L29/7869

Abstract: An embodiment of the disclosure provides an array substrate comprising: a base substrate, an active layer and a transparent electrode disposed on the base substrate, an etch stop layer disposed on the active layer and configured for protecting a portion of the active layer, wherein the active layer, the transparent electrode and the etch stop layer are formed through one patterning process and one doping process, the doped region and the first transparent electrode are made of same material and are disposed on the same layer.

公开(公告)号：US09502577B2

公开(公告)日：2016-11-22

申请号：US14416227

申请日：2014-04-16

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Ke Wang ,  Seongyeol Yoo ,  Ce Ning ,  Wei Yang

IPC: H01L29/786 ,  H01L21/4763 ,  H01L29/51 ,  H01L29/49 ,  H01L29/66 ,  H01L29/423 ,  H01L29/417

CPC classification number: H01L29/7869 ,  H01L21/47635 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66969 ,  H01L29/78606

Abstract: Provided are oxide thin-film transistor and display device employing the same, and method for manufacturing an oxide thin-film transistor array substrate. A source electrode and a drain electrode are located below an oxide active layer pattern, and a gate electrode is located below the source electrode and the drain electrode, and the gate insulating layer is located between the gate electrode and the source electrode/the drain electrode.

Abstract translation: 提供了氧化物薄膜晶体管和采用该氧化物薄膜晶体管的显示装置，以及制造氧化物薄膜晶体管阵列基板的方法。 源电极和漏极位于氧化物有源层图案的下方，栅电极位于源极和漏电极的下方，栅极绝缘层位于栅电极和源电极/漏电极之间 。