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228 条记录 (耗时 0.048 秒)

    Method and system for storing and processing multiple memory addresses
    91.
    发明授权
    Method and system for storing and processing multiple memory addresses 失效

    公开(公告)号：US5825711A

    公开(公告)日：1998-10-20

    申请号：US874973

    申请日：1997-06-13

    申请人： Troy A. Manning

    发明人： Troy A. Manning

    IPC分类号： G11C11/407 ,  G11C5/06 ,  G11C7/10 ,  G11C11/401 ,  G11C8/00 ,  G11C7/00

    CPC分类号： G11C7/1018 ,  G11C5/066 ,  G11C7/1072

    摘要： A packetized dynamic random access memory ("DRAM") receives command packets each of which contain a plurality of command words. One of the command words in each command packet includes a column address. Each of the command words, including the column address, is stored in one of a plurality of storage units so that a plurality of column addresses may be simultaneously stored in the storage units. The column addresses are individually coupled from respective storage units to a common column address bus which includes an address latch. The column address bus drives a column address processing circuit, such as a column address decoder. Also included is an adder that allows the DRAM to operate in a burst mode. In response to receiving an increment signal, the adder increments the column address at the output of the column address bus and applies the incremented address to the input of the column address bus.

    Memory device with distributed voltage regulation system
    92.
    发明授权
    Memory device with distributed voltage regulation system 失效

    公开(公告)号：US5818780A

    公开(公告)日：1998-10-06

    申请号：US717170

    申请日：1996-09-20

    申请人： Troy A. Manning

    发明人： Troy A. Manning

    IPC分类号： G11C5/14 ,  G11C8/00

    CPC分类号： G11C5/147

    摘要： A memory device includes a memory cell array, control circuits, and a voltage regulation system. The voltage regulation system includes an array power bus distributing an array supply voltage to the array, and a control circuit power bus distributing a control circuit supply voltage to the control circuits. Regulator circuits are coupled to the array power bus at spaced-apart locations along the bus which allow each regulator circuit to respond independently to a localized variation in the array supply voltage. Other regulator circuits are similarly coupled to the control circuit power bus. The regulator circuits which are unneeded for a particular operating mode of the memory device can be turned off during active memory cycles, and all the regulator circuits can be turned off during stand-by memory cycles. A resistor couples the array and control circuit power busses, and a low-power regulator circuit is coupled to the control circuit power bus to maintain both the array and control circuit supply voltages during stand-by memory cycles while the regulator circuits are off. The voltage regulation system thus advantageously reduces the power consumption of the memory device by using the low-power regulator circuit alone during stand-by memory cycles, reduces noise from the array on the control circuit supply voltage by splitting the array and control circuit power busses, and provides more responsive regulation of the array and control circuit supply voltages by distributing the regulator circuits.

    Address transition detection on a synchronous design
    93.
    发明授权
    Address transition detection on a synchronous design 失效
    同步设计中的地址转换检测

    公开(公告)号：US5729503A

    公开(公告)日：1998-03-17

    申请号：US506438

    申请日：1995-07-24

    申请人： Troy A. Manning

    发明人： Troy A. Manning

    IPC分类号： G06F12/06 ,  G11C7/10 ,  G11C11/407 ,  G11C8/00

    CPC分类号： G06F12/0638 ,  G11C11/407 ,  G11C7/1018 ,  G11C7/1021 ,  G11C7/1024 ,  G11C7/1039 ,  G11C7/1045 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/1096 ,  G06F2212/2022

    摘要： An integrated circuit memory device is designed to perform high speed burst access read and write cycles. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. A transition of the Read/Write control line during a burst access is used to terminate the burst access and initialize the device for another burst access. The memory device maintains compatibility with nonburst mode devices such as Extended Data Out (EDO) and Fast Page Mode through bond option or mode selection circuitry. A multiplexer selects between the input address and the burst address generator output to feed an asynchronous address transition detection circuit. The address transition detection circuit generates an equilibration control signal between memory access cycles.

    摘要翻译： 集成电路存储器件被设计为执行高速脉冲串访问读和写周期。 地址选通信号用于锁存第一个地址。 在突发访问周期期间，地址在设备内部增加，并具有额外的地址选通转换。 只有在每次突发访问开始时才需要新的内存地址。 读/写命令每次突发存取发出一次，无需在器件周期频率下切换读/写控制线。 在脉冲串访问期间读/写控制线的转换用于终止脉冲串访问并初始化该设备以进行另一脉冲串访问。 存储器件通过接合选项或模式选择电路保持与非突发模式器件的兼容性，例如扩展数据输出（EDO）和快速寻呼模式。 多路复用器在输入地址和突发地址发生器输出之间选择馈送异步地址转换检测电路。 地址转换检测电路在存储器访问周期之间产生平衡控制信号。

    Counter control circuit in a burst memory
    94.
    发明授权
    Counter control circuit in a burst memory 失效
    突发存储器中的计数器控制电路

    公开(公告)号：US5721859A

    公开(公告)日：1998-02-24

    申请号：US553156

    申请日：1995-11-07

    申请人： Troy A. Manning

    发明人： Troy A. Manning

    IPC分类号： G06F12/06 ,  G11C7/10 ,  G11C11/407 ,  G06F9/26 ,  G06F12/00

    CPC分类号： G11C7/109 ,  G06F12/0638 ,  G11C11/407 ,  G11C7/1021 ,  G11C7/1024 ,  G11C7/1039 ,  G11C7/1045 ,  G11C7/1078 ,  G11C7/1096 ,  G06F2212/2022

    摘要： An integrated memory circuit is described which can be operated in a burst access mode. The memory circuit includes an address counter which changes column addresses in one of a number of predetermined patterns. The column address is changes in response to a rising edge of a column address signal (CAS*). The memory also includes a buffer circuit which latches the output of the address counter in response to the falling edge of the column address signal. Memory cells are accessed in a burst manner on the falling edge of the column address signal using the address latched in the buffer.

    摘要翻译： 描述了可以以突发接入模式操作的集成存储器电路。 存储器电路包括地址计数器，其以多个预定模式之一改变列地址。 列地址响应列地址信号（CAS *）的上升沿而改变。 存储器还包括缓冲电路，其响应于列地址信号的下降沿而锁存地址计数器的输出。 使用在缓冲器中锁存的地址，在列地址信号的下降沿以突发方式访问存储单元。

    Burst EDO memory device address counter
    95.
    发明授权
    Burst EDO memory device address counter 失效
    突发EDO存储设备地址计数器

    公开(公告)号：US5675549A

    公开(公告)日：1997-10-07

    申请号：US457651

    申请日：1995-06-01

    申请人： Adrian Ong ,  Paul S. Zagar ,  Brett L. Wiliams ,  Troy A. Manning

    发明人： Adrian Ong ,  Paul S. Zagar ,  Brett L. Wiliams ,  Troy A. Manning

    IPC分类号： G06F12/06 ,  G11C7/10 ,  G11C11/407 ,  G11C8/00

    CPC分类号： G06F12/0638 ,  G11C11/407 ,  G11C7/1018 ,  G11C7/1021 ,  G11C7/1024 ,  G11C7/1039 ,  G11C7/1045 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/1096 ,  G06F2212/2022

    摘要： A counter comprised of two flip flops and a multiplexer produces a sequential or interleaved address sequence. The addresses produced are used to access memory elements in a Burst Extended Data Output Dynamic Random Access Memory (Burst EDO or BEDO DRAM). Input addresses in combination with a sequence select signal are logically combined to produce a multiplexer select input which selects between true and compliment outputs of a first flip flop to couple to an input of a second flip flop to specify a toggle condition for the second flip flop. Outputs of the counter are compared with outputs of an input address latch to detect the end of a burst sequence and initialize the device for another burst access. A transition of the Read/Write control line during a burst access will terminate the burst access and initialize the device for another burst access.

    摘要翻译： 由两个触发器和多路复用器组成的计数器产生顺序或交错地址序列。 所产生的地址用于访问突发扩展数据输出动态随机存取存储器（Burst EDO或BEDO DRAM）中的存储器元件。 与序列选择信号组合的输入地址被逻辑地组合以产生多路复用器选择输入，其选择第一触发器的真实和补码输出以耦合到第二触发器的输入以指定第二触发器的切换条件 。 将计数器的输出与输入地址锁存器的输出进行比较，以检测突发序列的结束，并初始化用于另一个突发存取的设备。 在脉冲串访问期间读/写控制线的转换将终止脉冲串访问并初始化设备以进行另一个突发存取。

    Data compression and management
    96.
    发明授权
    Data compression and management 有权
    数据压缩和管理

    公开(公告)号：US09148172B2

    公开(公告)日：2015-09-29

    申请号：US13531090

    申请日：2012-06-22

    申请人： Troy A. Manning ,  Troy D. Larsen ,  Martin L. Culley ,  Jeffrey L. Meader ,  Steve G. Bard ,  Dean C. Eyres

    发明人： Troy A. Manning ,  Troy D. Larsen ,  Martin L. Culley ,  Jeffrey L. Meader ,  Steve G. Bard ,  Dean C. Eyres

    IPC分类号： H03M7/30

    CPC分类号： G06F3/0608 ,  G06F3/0661 ,  G06F3/0673 ,  H03M7/30 ,  H03M7/60 ,  H03M7/6082

    摘要： The present disclosure includes apparatuses and methods for data compression and management. A number of methods include receiving a number of data segments corresponding to a managed unit amount of data, determining a respective compressibility of each of the number of data segments, compressing each of the number of data segments in accordance with its respective determined compressibility, forming a compressed managed unit that includes compressed and/or uncompressed data segments corresponding to the number of data segments corresponding to the managed unit amount of data, and forming a page of data that comprises at least the compressed managed unit.

    摘要翻译： 本公开包括用于数据压缩和管理的装置和方法。 多种方法包括接收对应于被管理单元数据量的多个数据段，确定多个数据段中的每一个的相应可压缩性，根据其各自确定的压缩性来压缩数据段中的每一个，形成 压缩的被管理单元，其包括对应于与被管理单元数据量对应的数据段的数量的压缩和/或未压缩数据段，以及形成至少包括压缩的被管理单元的数据页。