公开(公告)号：US20080096330A1

公开(公告)日：2008-04-24

申请号：US11958877

申请日：2007-12-18

申请人： Bruce Doris ,  Kathryn Guarini ,  Meikei Ieong ,  Shreesh Narasimha ,  Kern Rim ,  Jeffrey Sleight ,  Min Yang

发明人： Bruce Doris ,  Kathryn Guarini ,  Meikei Ieong ,  Shreesh Narasimha ,  Kern Rim ,  Jeffrey Sleight ,  Min Yang

IPC分类号： H01L21/84

CPC分类号： H01L21/76275 ,  H01L21/823807 ,  H01L21/84

摘要： An integrated semiconductor structure containing at least one device formed upon a first crystallographic surface that is optimal for that device, while another device is formed upon a second different crystallographic surface that is optimal for the other device is provided. The method of forming the integrated structure includes providing a bonded substrate including at least a first semiconductor layer of a first crystallographic orientation and a second semiconductor layer of a second different crystallographic orientation. A portion of the bonded substrate is protected to define a first device area, while another portion of the bonded substrate is unprotected. The unprotected portion of the bonded substrate is then etched to expose a surface of the second semiconductor layer and a semiconductor material is regrown on the exposed surface. Following planarization, a first semiconductor device is formed in the first device region and a second semiconductor device is formed on the regrown material.

摘要翻译： 提供包含至少一个器件的集成半导体结构，所述器件形成在对于该器件最佳的第一晶体表面上，而另一器件形成在对于另一器件最佳的第二不同晶体表面上。 形成集成结构的方法包括提供包括至少第一晶体取向的第一半导体层和第二不同晶体取向的第二半导体层的键合衬底。 键合衬底的一部分被保护以限定第一器件区域，而键合衬底的另一部分是未受保护的。 然后蚀刻键合衬底的未保护部分以暴露第二半导体层的表面，并将半导体材料重新生长在暴露表面上。 在平坦化之后，在第一器件区域中形成第一半导体器件，并且在再生长材料上形成第二半导体器件。

公开(公告)号：US20080026522A1

公开(公告)日：2008-01-31

申请号：US11867271

申请日：2007-10-04

申请人： Bruce Doris ,  Dureseti Chidambarrao ,  Suk Ku

发明人： Bruce Doris ,  Dureseti Chidambarrao ,  Suk Ku

IPC分类号： H01L21/8238

CPC分类号： H01L29/7842 ,  H01L21/823864 ,  H01L29/7843 ,  Y10S257/90 ,  Y10S438/938

摘要： A semiconductor device structure includes at least two field effect transistors formed on same substrate, the first field effect transistor includes a spacer having a first width, the second field effect transistor includes a compressive spacer having a second width, the first width being different than said second width. Preferably, the first width is narrower than the second width. A tensile stress dielectric film forms a barrier etch stop layer over the transistors.

摘要翻译： 半导体器件结构包括形成在同一衬底上的至少两个场效应晶体管，第一场效应晶体管包括具有第一宽度的间隔物，第二场效应晶体管包括具有第二宽度的压缩间隔物，第一宽度不同于所述第一宽度 第二宽度。 优选地，第一宽度比第二宽度窄。 拉伸应力介电膜在晶体管上形成阻挡蚀刻停止层。

公开(公告)号：US20070173008A1

公开(公告)日：2007-07-26

申请号：US11336727

申请日：2006-01-20

申请人： Michael Chudzik ,  Bruce Doris ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri ,  Yun Wang ,  Keith Wong

发明人： Michael Chudzik ,  Bruce Doris ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri ,  Yun Wang ,  Keith Wong

IPC分类号： H01L21/8238

CPC分类号： H01L29/517 ,  H01L21/28088 ,  H01L21/823828 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor structures, such as, for example, field effect transistors (FETs) and/or metal-oxide-semiconductor capacitor (MOSCAPs), are provided in which the workfunction of a conductive electrode stack is changed by introducing metal impurities into a metal-containing material layer which, together with a conductive electrode, is present in the electrode stack. The choice of metal impurities depends on whether the electrode is to have an n-type workfunction or a p-type workfunction. The present invention also provides a method of fabricating such semiconductor structures. The introduction of metal impurities can be achieved by codeposition of a layer containing both a metal-containing material and workfunction altering metal impurities, forming a stack in which a layer of metal impurities is present between layers of a metal-containing material, or by forming a material layer including the metal impurities above and/or below a metal-containing material and then heating the structure so that the metal impurities are introduced into the metal-containing material.

摘要翻译： 提供半导体结构，例如场效应晶体管（FET）和/或金属氧化物半导体电容器（MOSCAP），其中通过将金属杂质引入到含金属的物质中来改变导电电极堆叠的功函数 材料层与导电电极一起存在于电极堆叠中。 金属杂质的选择取决于电极是否具有n型功函数或p型功函数。 本发明还提供一种制造这种半导体结构的方法。 金属杂质的引入可以通过共沉积含有金属的材料和改变金属杂质的功函数的层来形成，形成其中金属杂质层存在于含金属材料的层之间的叠层，或通过形成 包括在含金属材料上方和/或下面的金属杂质的材料层，然后加热该结构，使得金属杂质被引入到含金属的材料中。

公开(公告)号：US20070138556A1

公开(公告)日：2007-06-21

申请号：US11676030

申请日：2007-02-16

申请人： Omer Dokumaci ,  Bruce Doris ,  Kathryn Guarini ,  Suryanarayan Hegde ,  Meikei Ieong ,  Erin Jones

发明人： Omer Dokumaci ,  Bruce Doris ,  Kathryn Guarini ,  Suryanarayan Hegde ,  Meikei Ieong ,  Erin Jones

IPC分类号： H01L27/12

CPC分类号： H01L29/78648 ,  H01L21/0338 ,  H01L21/2007 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/42384

摘要： A double-gate transistor has front (upper) and back gates aligned laterally by a process of forming symmetric sidewalls in proximity to the front gate and then oxidizing the back gate electrode at a temperature of at least 1000 degrees for a time sufficient to relieve stress in the structure, the oxide penetrating from the side of the transistor body to thicken the back gate oxide on the outer edges, leaving an effective thickness of gate oxide at the center, aligned with the front gate electrode. Optionally, an angled implant from the sides of an oxide enhancing species encourages relatively thicker oxide in the outer implanted areas and an oxide-retarding implant across the transistor body retards oxidation in the vertical direction, thereby permitting increase of the lateral extent of the oxidation.

摘要翻译： 双栅极晶体管具有通过在前栅极附近形成对称侧壁然后在至少1000度的温度下氧化背栅电极足以缓解应力的时间的方法横向排列的前（上）和后门 在该结构中，氧化物从晶体管主体的侧面渗透，以增厚外边缘上的背栅氧化层，留下中心的栅极氧化物的有效厚度，与前栅电极对准。 任选地，来自氧化物增强物质的侧面的成角度的植入物鼓励外部注入区域中相对较厚的氧化物，并且跨越晶体管体的氧化物延迟植入阻碍垂直方向上的氧化，从而允许增加氧化的横向范围。

公开(公告)号：US20060148147A1

公开(公告)日：2006-07-06

申请号：US11362773

申请日：2006-02-28

申请人： Michael Belyansky ,  Bruce Doris ,  Oleg Gluschenkov

发明人： Michael Belyansky ,  Bruce Doris ,  Oleg Gluschenkov

IPC分类号： H01L21/338

CPC分类号： H01L29/0653 ,  H01L29/66636 ,  H01L29/7848

摘要： Compressive or tensile materials are selectively introduced beneath and in alignment with spacer areas and adjacent to channel areas of a semiconductor substrate to enhance or degrade electron and hole mobility in CMOS circuits. A process entails steps of creating dummy spacers, forming a dielectric mandrel (i.e., mask), removing the dummy spacers, etching recesses into the underlying semiconductor substrate, introducing a compressive or tensile material into a portion of each recess, and filling the remainder of each recess with substrate material.

公开(公告)号：US20060148143A1

公开(公告)日：2006-07-06

申请号：US10905477

申请日：2005-01-06

申请人： Stephen Bedell ,  Bruce Doris ,  Devendra Sadana

发明人： Stephen Bedell ,  Bruce Doris ,  Devendra Sadana

IPC分类号： H01L21/84 ,  H01L21/00 ,  H01L21/20

CPC分类号： H01L21/26506 ,  H01L21/26566 ,  H01L21/2658 ,  H01L21/84 ,  H01L29/1054 ,  H01L29/51 ,  H01L29/66575 ,  H01L29/78687

摘要： A method of forming a surface Ge-containing channel which can be used to fabricate a Ge-based field effect transistor (FET) which can be applied to semiconductor-on-insulator substrates (SOIs) is provided. The disclosed method uses Ge-containing ion beams, such as cluster ion beams, to create a strained Ge-containing rich region at or near a surface of a SOI substrate. The Ge-containing rich region can be present continuously across the entire surface of the semiconductor substrate, or it can be present as a discrete region at a predetermined surface portion of the semiconductor substrate.

摘要翻译： 提供了可用于制造可应用于绝缘体上半导体衬底（SOI）的基于Ge的场效应晶体管（FET）的表面Ge含有沟道的形成方法。 所公开的方法使用含Ge离子束，例如簇离子束，以在SOI衬底的表面处或附近产生应变的含Ge富集区。 含锗富含区域可以连续地存在于半导体衬底的整个表面上，或者可以作为半导体衬底的预定表面部分处的离散区域存在。

公开(公告)号：US20060057787A1

公开(公告)日：2006-03-16

申请号：US10536483

申请日：2002-11-25

申请人： Bruce Doris ,  Dureseti Chidambarrao ,  Meikei Leong ,  Jack Mandelman

发明人： Bruce Doris ,  Dureseti Chidambarrao ,  Meikei Leong ,  Jack Mandelman

IPC分类号： H01L21/84 ,  H01L27/12

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L29/7843 ,  H01L29/785

摘要： A semiconductor device structure, includes a PMOS device 200 and an NMOS device 300 disposed on a substrate 1,2, the PMOS device including a compressive layer 6 stressing an active region of the PMOS device, the NMOS device including a tensile layer 9 stressing an active region of the NMOS device, wherein the compressive layer includes a first dielectric material, the tensile layer includes a second dielectric material, and the PMOS and NMOS devices are FinFET devices 200, 300.

摘要翻译： 半导体器件结构包括PMOS器件200和设置在衬底1,2上的NMOS器件300，PMOS器件包括压迫PMOS器件的有源区的压缩层6，NMOS器件包括拉伸层9， 所述NMOS器件的有源区，其中所述压缩层包括第一介电材料，所述拉伸层包括第二介电材料，并且所述PMOS和NMOS器件为FinFET器件200,300。

公开(公告)号：US20050280121A1

公开(公告)日：2005-12-22

申请号：US10872605

申请日：2004-06-21

申请人： Bruce Doris ,  Meikei Ieong ,  Edward Nowak ,  Min Yang

发明人： Bruce Doris ,  Meikei Ieong ,  Edward Nowak ,  Min Yang

IPC分类号： H01L21/20 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/04 ,  H01L29/76

CPC分类号： H01L21/76251 ,  H01L21/76243 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/045 ,  H01L29/785

摘要： A hybrid substrate having a high-mobility surface for use with planar and/or multiple-gate metal oxide semiconductor field effect transistors (MOSFETs) is provided. The hybrid substrate has a first surface portion that is optimal for n-type devices, and a second surface portion that is optimal for p-type devices. Due to proper surface and wafer flat orientations in each semiconductor layers of the hybrid substrate, all gates of the devices are oriented in the same direction and all channels are located on the high mobility surface. The present invention also provides for a method of fabricating the hybrid substrate as well as a method of integrating at least one planar or multiple-gate MOSFET thereon.

摘要翻译： 提供了具有用于平面和/或多栅极金属氧化物半导体场效应晶体管（MOSFET）的高迁移率表面的混合衬底。 混合基板具有对于n型器件是最佳的第一表面部分和对于p型器件是最佳的第二表面部分。 由于混合衬底的每个半导体层中的适当的表面和晶片平坦取向，器件的所有栅极被定向在相同的方向上，并且所有沟道都位于高迁移率表面上。 本发明还提供了一种制造混合衬底的方法以及在其上集成至少一个平面或多栅极MOSFET的方法。

公开(公告)号：US20050245008A1

公开(公告)日：2005-11-03

申请号：US10709314

申请日：2004-04-28

申请人： Bruce Doris ,  Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger

发明人： Bruce Doris ,  Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger

IPC分类号： H01L21/00 ,  H01L21/20 ,  H01L21/28 ,  H01L21/31 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/44 ,  H01L21/469 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/49

CPC分类号： H01L21/823437 ,  H01L21/28097 ,  H01L21/28123 ,  H01L21/32139 ,  H01L29/4975

摘要： A method for forming a gate structure for a semiconductor device includes defining a conductive sacrificial structure on a substrate, forming a reacted metal film on sidewalls of the conductive sacrificial structure, and removing unreacted portions of the conductive sacrificial structure.

摘要翻译： 用于形成半导体器件的栅极结构的方法包括在衬底上限定导电牺牲结构，在导电牺牲结构的侧壁上形成反应的金属膜，以及去除导电牺牲结构的未反应部分。

公开(公告)号：US20050236687A1

公开(公告)日：2005-10-27

申请号：US10830347

申请日：2004-04-22

申请人： Kevin Chan ,  Bruce Doris ,  Kathryn Guarini ,  Meikei Ieong ,  Shreesh Narasimha ,  Alexander Reznicek ,  Kern Rim ,  Devendra Sadana ,  Leathen Shi ,  Jeffrey Sleight ,  Min Yang

发明人： Kevin Chan ,  Bruce Doris ,  Kathryn Guarini ,  Meikei Ieong ,  Shreesh Narasimha ,  Alexander Reznicek ,  Kern Rim ,  Devendra Sadana ,  Leathen Shi ,  Jeffrey Sleight ,  Min Yang

IPC分类号： H01L27/08 ,  H01L21/02 ,  H01L21/20 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/04 ,  H01L29/76 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/7842 ,  H01L21/2022 ,  H01L21/76275 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/78687

摘要： Methods of forming a strained Si-containing hybrid substrate are provided as well as the strained Si-containing hybrid substrate formed by the methods. In the methods of the present invention, a strained Si layer is formed overlying a regrown semiconductor material, a second semiconducting layer, or both. In accordance with the present invention, the strained Si layer has the same crystallographic orientation as either the regrown semiconductor layer or the second semiconducting layer. The methods provide a hybrid substrate in which at least one of the device layers includes strained Si.

摘要翻译： 提供了形成应变含Si的杂化基板的方法以及通过这些方法形成的应变的含Si杂化基板。 在本发明的方法中，形成覆盖重新生长的半导体材料，第二半导体层或两者的应变Si层。 根据本发明，应变Si层具有与再生长半导体层或第二半导电层相同的晶体取向。 该方法提供混合基板，其中至少一个器件层包括应变Si。