公开(公告)号：US20100044759A1

公开(公告)日：2010-02-25

申请号：US12612957

申请日：2009-11-05

申请人： Kerry Bernstein ,  Timothy Dalton ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Paul David Kartschoke ,  Stephen Ellinwood Luce ,  Anthony Kendall Stamper

发明人： Kerry Bernstein ,  Timothy Dalton ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Paul David Kartschoke ,  Stephen Ellinwood Luce ,  Anthony Kendall Stamper

IPC分类号： H01L29/786 ,  H01L21/18 ,  H01L21/768 ,  H01L23/48

CPC分类号： H01L25/0657 ,  H01L21/76895 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5329 ,  H01L25/50 ,  H01L27/0688 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure and method of fabricating the structure. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.

摘要翻译： 一种半导体结构及其制造方法。 该方法包括从具有在其中制造的器件的两个绝缘体上硅晶片上去除背面硅，并利用掩埋氧化物层将它们背对背地接合。 然后在上晶片中形成与下晶片中的器件接触，并在上晶片上形成布线层。 下晶片可以包括布线​​水平。 下部晶片可以包括用于触点的着陆焊盘。 与下晶片的硅层的接触可以被硅化。

公开(公告)号：US20090308578A1

公开(公告)日：2009-12-17

申请号：US12544344

申请日：2009-08-20

申请人： Kerry Bernstein ,  Thomas Brunschwiler ,  Bruno Michel

发明人： Kerry Bernstein ,  Thomas Brunschwiler ,  Bruno Michel

IPC分类号： F28D15/00

CPC分类号： H01L23/49827 ,  H01L23/46 ,  H01L23/473 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/15159 ,  H01L2924/3011

摘要： An assembly includes a chip including an integrated circuit, a casing including an integrated circuit and having an upper portion formed on a side of the chip and lower portion formed on another side of the chip, plural through-wafer vias (TWVs) for electrically connecting the integrated circuit of the chip and the integrated circuit of the casing, and a card connected to the casing for electrically connecting the casing to a system board.

公开(公告)号：US20090224803A1

公开(公告)日：2009-09-10

申请号：US12045500

申请日：2008-03-10

申请人： Kerry Bernstein ,  Andres Bryant ,  Wilfried Haensch

发明人： Kerry Bernstein ,  Andres Bryant ,  Wilfried Haensch

IPC分类号： H03K19/20

CPC分类号： H03K19/0008 ,  H03K3/356104 ,  H03K2217/0018

摘要： A novel methodology for the construction and operation of logical circuits and gates that make use of and contact to a fourth terminal (substrates/bodies) of MOSFET devices is described in detail. The novel construction and operation provides for maintaining such body-contacted MOSFET devices at a lower threshold voltage (VTh) when actively on (to increase overdrive and performance), and at a higher relative threshold voltage when off (to reduce leakage power). Because the threshold potential of a gate moves inversely to its body potential, it follows then that in general, the body of a given device must be tied to the inverse of the device's drain voltage to achieve such a desirable threshold potential modulation effect for improved device, circuit, gate and logical family operation.

公开(公告)号：US07521950B2

公开(公告)日：2009-04-21

申请号：US11163167

申请日：2005-10-07

申请人： Kerry Bernstein ,  Paul Coteus ,  Ibrahim M. Elfadel ,  Philip Emma ,  Daniel J. Friedman ,  Ruchir Puri ,  Mark B. Ritter ,  Jeannine Trewhella ,  Albert M. Young

发明人： Kerry Bernstein ,  Paul Coteus ,  Ibrahim M. Elfadel ,  Philip Emma ,  Daniel J. Friedman ,  Ruchir Puri ,  Mark B. Ritter ,  Jeannine Trewhella ,  Albert M. Young

IPC分类号： G01R31/02 ,  G01R31/26 ,  G01R31/28 ,  G01R31/00 ,  G01N37/00 ,  G06F13/20 ,  G06F13/36 ,  G06F11/00

CPC分类号： G11C29/006 ,  G11C29/12 ,  G11C29/1201 ,  G11C2029/1206

摘要： A 3D chip having at least one I/O layer connected to other 3D chip layers by a vertical bus such that the I/O layer(s) may accommodate protection and off-chip device drive circuits, customization circuits, translation circuits, conversions circuits and/or built-in self-test circuits capable of comprehensive chip or wafer level testing wherein the I/O layers function as a testhead. Substitution of I/O circuits or structures may be performed using E-fuses or the like responsive to such testing.

摘要翻译： 具有至少一个I / O层的3D芯片，其通过垂直总线连接到其他3D芯片层，使得所述I / O层可适应保护和芯片外设备驱动电路，定制电路，平移电路，转换电路 和/或能够进行全面的芯片或晶片级测试的内置自检电路，其中I / O层用作测试头。 I / O电路或结构的替代可以使用响应于这种测试的电子熔断器等进行。

公开(公告)号：US20080291767A1

公开(公告)日：2008-11-27

申请号：US11751315

申请日：2007-05-21

申请人： Joseph S. Barnes ,  Jagreet S. Atwal ,  Kerry Bernstein ,  Robert J. Bucki

发明人： Joseph S. Barnes ,  Jagreet S. Atwal ,  Kerry Bernstein ,  Robert J. Bucki

IPC分类号： G11C8/00 ,  H01L21/4763

CPC分类号： H01L21/8221 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/1203

摘要： A multi-port register file (e.g., memory element) is provided in which each read port of the register file is located in a separate wafer above and/or below the primary data storage element. This is achieved in the present invention by utilizing three-dimensional integration in which multiple active circuit layers are vertically stacked and vertically aligned interconnects are employed to connect a device from one of the stacked layers to another device in another stacked layer.

摘要翻译： 提供多端口寄存器文件（例如，存储器元件），其中寄存器堆的每个读端口位于主数据存储元件上方和/或下方的单独晶片中。 这在本发明中通过利用三维积分来实现，其中多个有源电路层被垂直堆叠并且使用垂直排列的互连将装置从堆叠层之一连接到另一层叠层中的另一装置。

公开(公告)号：US20080285338A1

公开(公告)日：2008-11-20

申请号：US12180776

申请日：2008-07-28

申请人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith R. Williams

发明人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith R. Williams

IPC分类号： G11C11/34

CPC分类号： G11C11/417

摘要： A system, method and program product for determining a history state of data in a data retaining device are disclosed. A state of a partially-depleted silicon-on-insulator (PD SOI) device coupled to a data retaining device is measured to indicate a body voltage of the PD SOI device. The body voltage of the PD SOI device may indicate, among others, how long the PD SOI device has been idling, which indirectly indicates how long data in the data retaining device has not been accessed. As such, the current invention may be used efficiently with, e.g., a cache replacement algorithm in a management of the data retaining device.

摘要翻译： 公开了一种用于确定数据保持装置中的数据的历史状态的系统，方法和程序产品。 耦合到数据保持装置的部分耗尽的绝缘体上硅（PD SOI）器件的状态被测量以指示PD SOI器件的体电压。 PD SOI器件的体电压可以指示PD SOI器件已经空转多长时间，这间接地指示数据保持器件中的数据未被访问多长时间。 因此，本发明可以在数据保留装置的管理中与例如高速缓存替换算法有效地使用。

公开(公告)号：US20080203445A1

公开(公告)日：2008-08-28

申请号：US12120899

申请日：2008-05-15

申请人： Kerry Bernstein ,  Paul W. Coteus ,  Philip George Emma ,  Allan Mark Hartstein ,  Stephen V. Kosonocky ,  Ruchir Puri ,  Mark B. Ritter

发明人： Kerry Bernstein ,  Paul W. Coteus ,  Philip George Emma ,  Allan Mark Hartstein ,  Stephen V. Kosonocky ,  Ruchir Puri ,  Mark B. Ritter

IPC分类号： H01L29/80

CPC分类号： G11C5/063 ,  G11C5/14 ,  H01L21/8221 ,  H01L27/0688 ,  H03H1/0007

摘要： An IC structure having reduced power loss and/or noise includes two or more active semiconductor regions stacked in a substantially vertical dimension, each active semiconductor region including an active layer. The IC structure further includes two or more voltage supply planes, each of the voltage supply planes corresponding to a respective one of the active layers.

摘要翻译： 具有降低的功率损耗和/或噪声的IC结构包括以基本上垂直的尺寸堆叠的两个或更多个有源半导体区域，每个有源半导体区域包括有源层。 IC结构还包括两个或更多个电压供应平面，每个电压供应平面对应于相应的一个有源层。

公开(公告)号：US20080195987A1

公开(公告)日：2008-08-14

申请号：US12103038

申请日：2008-04-15

申请人： Kerry Bernstein ,  Norman J. Rohrer

发明人： Kerry Bernstein ,  Norman J. Rohrer

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  H03K19/0016 ,  H03K19/0948

摘要： A computer system for designing a low leakage monotonic CMOS logic circuit. The system performing the computer implements steps of: (a) specifying a reference PFET having its threshold voltage and its gate dielectric thickness and a reference NFET having its threshold voltage and its gate dielectric thickness; (b) synthesizing a schematic circuit design with standard design elements, the standard design elements including one or more reference PFETS and one or more reference NFETs; (c) analyzing one or more circuits for logic stages having predominantly high input logic states or predominantly low input logic states; (d) selecting one or more logic stages determined to have predominantly high input logic states or predominantly low input logic states; and (e) replacing the standard design elements of the selected logic stages with reduced current leakage elements.

摘要翻译： 一种用于设计低泄漏单调CMOS逻辑电路的计算机系统。 执行计算机的系统实现以下步骤：（a）指定具有其阈值电压及其栅介质厚度的参考PFET和具有其阈值电压及其栅介质厚度的参考NFET; （b）用标准设计元件合成示意电路设计，标准设计元件包括一个或多个参考PFET和一个或多个参考NFET; （c）分析具有主要为高输入逻辑状态或主要为低输入逻辑状态的逻辑级的一个或多个电路; （d）选择确定为具有主要高输入逻辑状态或主要为低输入逻辑状态的一个或多个逻辑级; 和（e）用减少的电流泄漏元件代替所选逻辑级的标准设计元件。

公开(公告)号：US07402854B2

公开(公告)日：2008-07-22

申请号：US11496120

申请日：2006-07-31

申请人： Kerry Bernstein ,  Paul W. Coteus ,  Philip George Emma ,  Allan Mark Hartstein ,  Stephen V. Kosonocky ,  Ruchir Puri ,  Mark B. Ritter

发明人： Kerry Bernstein ,  Paul W. Coteus ,  Philip George Emma ,  Allan Mark Hartstein ,  Stephen V. Kosonocky ,  Ruchir Puri ,  Mark B. Ritter

IPC分类号： H01L29/80

CPC分类号： G11C5/063 ,  G11C5/14 ,  H01L21/8221 ,  H01L27/0688 ,  H03H1/0007

摘要： An IC structure having reduced power loss and/or noise includes two or more active semiconductor regions stacked in a substantially vertical dimension, each active semiconductor region including an active layer. The IC structure further includes two or more voltage supply planes, each of the voltage supply planes corresponding to a respective one of the active layers.

公开(公告)号：US20080151672A1

公开(公告)日：2008-06-26

申请号：US12045744

申请日：2008-03-11

申请人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith R. Williams

发明人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith R. Williams

IPC分类号： G11C7/00

CPC分类号： G06F12/121 ,  G06F12/122

摘要： A system, method and program product for determining a relative amount of usage of a data retaining device are disclosed. A charge storing device is coupled to a data retaining device in a manner that a use of the data retaining device triggers a charging of the charge storing device. In a period that the data retaining device idles, charges in the charge storing device decay due to natural means. As such, a potential of the charge storing device may be used to indicate an amount of usage of the data retaining device. A comparison of the potentials of two charge storing devices coupled one-to-one to two data retaining devices may be used as a basis to determine a relative amount of usage of each of the two data retaining devices comparing to the other.

摘要翻译： 公开了一种用于确定数据保留装置的相对使用量的系统，方法和程序产品。 电荷存储装置以数据保持装置的使用触发电荷存储装置的充电的方式耦合到数据保持装置。 在数据保持装置闲置的期间，由于自然的手段，电荷存储装置中的电荷衰减。 因此，可以使用电荷存储装置的电位来指示数据保持装置的使用量。 可以使用将一对一耦合到两个数据保持装置的两个电荷存储装置的电位的比较作为确定两个数据保持装置中的每一个相对于另一个的相对使用量的基础。