公开(公告)号：US07400006B1

公开(公告)日：2008-07-15

申请号：US11405958

申请日：2006-04-18

申请人： Darrell Rinerson ,  Steve Kuo-Ren Hsia ,  Wayne Kinney ,  Steven W. Longcor

发明人： Darrell Rinerson ,  Steve Kuo-Ren Hsia ,  Wayne Kinney ,  Steven W. Longcor

IPC分类号： H01L31/062

CPC分类号： H01L27/2418 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/003 ,  G11C2213/31 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/147 ,  H01L45/165

摘要： A multi-resistive state element that uses barrier electrodes is provided. If certain materials are used as electrodes, the electrodes can be used for multiple purposes. Oxides and nitrides are especially well suited for acting as a barrier layer, and possibly even an adhesion layer and a sacrificial layer.

摘要翻译： 提供了使用阻挡电极的多电阻状态元件。 如果使用某些材料作为电极，电极可用于多种用途。 氧化物和氮化物特别适用于作为阻挡层，甚至可能甚至粘附层和牺牲层。

公开(公告)号：US20110186803A1

公开(公告)日：2011-08-04

申请号：US12931967

申请日：2011-02-15

申请人： Darrell Rinerson ,  Wayne Kinney ,  Edmond R. Ward ,  Steve Kuo-Ren Hsia ,  Steven W. Longcor ,  Christophe J. Chevallier ,  John Sanchez ,  Philip F.S. Swab

发明人： Darrell Rinerson ,  Wayne Kinney ,  Edmond R. Ward ,  Steve Kuo-Ren Hsia ,  Steven W. Longcor ,  Christophe J. Chevallier ,  John Sanchez ,  Philip F.S. Swab

IPC分类号： H01L45/00

CPC分类号： H01L27/2463 ,  G11C11/16 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/009 ,  G11C2213/15 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/77 ,  G11C2213/79 ,  H01L27/24 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1633 ,  H01L45/1658

摘要： A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO3-LSCoO or LaNiO3-LNO) that is in contact with the CMO. The conductive oxide layer can be selected as a seed layer operative to provide a good lattice match with and/or a lower crystallization temperature for the CMO. The conductive oxide layer may also be in contact with a metal layer (e.g., Pt). The memory cell additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays, such as non-volatile two-terminal cross-point memory arrays.

摘要翻译： 公开了一种包括导电氧化物电极的存储单元。 存储单元包括用于将数据存储为多个电阻状态的存储元件。 存储元件包括与可包括一层或多层材料的电极接触的导电金属氧化物（CMO）（例如，钙钛矿）层。 这些材料层中的至少一层可以是与CMO接触的导电氧化物（例如，诸如LaSrCoO3-LSCoO或LaNiO3-LNO的钙钛矿）。 可以选择导电氧化物层作为晶种层，以为CMO提供良好的晶格匹配和/或较低的结晶温度。 导电氧化物层也可以与金属层（例如Pt）接触。 存储单元还具有非线性IV特性，这在某些阵列中是有利的，例如非易失性两端交叉点存储阵列。

公开(公告)号：US07038935B2

公开(公告)日：2006-05-02

申请号：US10634636

申请日：2003-08-04

申请人： Darrell Rinerson ,  Wayne Kinney ,  Steven W. Longcor ,  Edmond R. Ward ,  Steve Kuo-Ren Hsia ,  Christophe J. Chevallier

发明人： Darrell Rinerson ,  Wayne Kinney ,  Steven W. Longcor ,  Edmond R. Ward ,  Steve Kuo-Ren Hsia ,  Christophe J. Chevallier

IPC分类号： G11C11/00 ,  H01L29/02

CPC分类号： G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/79 ,  H01L27/11502 ,  H01L27/11507 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/165

摘要： A 2-terminal trapped charge memory device is disclosed with voltage switchable multi-level resistance. The trapped charge memory device has a trapped charge memory body sandwiched between two electrodes. The trapped charge memory body can be made of a variety of semiconducting or insulating materials of single-crystalline, poly-crystalline or amorphous structure while containing current carrier traps whose respective energy levels and degrees of carrier occupancy, modifiable by the height and width of an applied write voltage pulse, determine the resistance. The mechanism of modification can be through carrier tunneling, free carrier capturing, trap-hopping conduction or Frenkel-Poole conduction. The current carrier traps can be created with dopant varieties or an initialization procedure.

摘要翻译： 公开了具有可电压切换的多电平电阻的2端子俘获电荷存储器件。 捕获的电荷存储器件具有夹在两个电极之间的俘获电荷存储器体。 捕获的电荷存储器主体可以由单晶，多晶或非晶结构的各种半导体或绝缘材料制成，同时包含其各自的能级和载体占有率的载流子阱，其可由 施加写电压脉冲，确定电阻。 修饰的机制可以通过载体隧穿，自由载体捕获，陷阱跳跃传导或Frenkel-Poole传导。 可以用掺杂剂品种或初始化程序产生当前载体陷阱。

公开(公告)号：US06917539B2

公开(公告)日：2005-07-12

申请号：US10360005

申请日：2003-02-07

申请人： Darrell Rinerson ,  Steven W. Longcor ,  Edmond R. Ward ,  Steve Kuo-Ren Hsia ,  Wayne Kinney

发明人： Darrell Rinerson ,  Steven W. Longcor ,  Edmond R. Ward ,  Steve Kuo-Ren Hsia ,  Wayne Kinney

IPC分类号： G11C11/56 ,  G11C13/00 ,  G11C11/14

CPC分类号： G11C13/0007 ,  G11C11/5685 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/77

摘要： High density NVRAM. An array of memory cells capable of storing at least a megabit of information, each memory cell including a memory plug that includes a memory element that switches from a first resistance state to a second resistance state upon application of a first write voltage of a first polarity and reversibly switches from the second resistance state to the first resistance state upon application of a second write voltage of polarity opposite to the first polarity.

摘要翻译： 高密度NVRAM。 一种能够存储至少一兆位信息的存储器单元阵列，每个存储器单元包括存储器插件，该存储器插件包括存储元件，该存储器元件在施加第一极性的第一写入电压时从第一电阻状态切换到第二电阻状态 并且当施加与第一极性相反的极性的第二写入电压时，可逆地从第二电阻状态切换到第一电阻状态。

公开(公告)号：US06906939B2

公开(公告)日：2005-06-14

申请号：US10612191

申请日：2003-07-01

申请人： Darrell Rinerson ,  Christophe J. Chevallier ,  Steven W. Longcor ,  Wayne Kinney ,  Edmond R. Ward

发明人： Darrell Rinerson ,  Christophe J. Chevallier ,  Steven W. Longcor ,  Wayne Kinney ,  Edmond R. Ward

IPC分类号： G11C11/56 ,  G11C13/00 ,  G11C16/02 ,  H01L27/24 ,  G11C5/06

CPC分类号： G11C13/0007 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C2213/31

摘要： A re-writable memory with multiple memory layers. Using both terminals of a memory cell in a stacked cross point structure for selection purposes allows multiple layers of conductive lines to be selected as long as there is only one memory cell that has two terminals selected. Sharing logic over multiple layers allows driver sets to be reused.

公开(公告)号：US06870755B2

公开(公告)日：2005-03-22

申请号：US10604556

申请日：2003-07-30

申请人： Darrell Rinerson ,  Christophe J. Chevallier ,  Steven W. Longcor ,  Wayne Kinney ,  Edmond R. Ward ,  Steve Kuo-Ren Hsia

发明人： Darrell Rinerson ,  Christophe J. Chevallier ,  Steven W. Longcor ,  Wayne Kinney ,  Edmond R. Ward ,  Steve Kuo-Ren Hsia

IPC分类号： G11C13/00 ,  G11C11/00

CPC分类号： G11C13/0007 ,  G11C13/003 ,  G11C2213/31 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/77

摘要： A re-writable memory that uses resistive memory cell elements with non-linear IV characteristics is disclosed. Non-linearity is important in certain memory arrays to prevent unselected cells from being disturbed and to reduce the required current. Non-linearity refers to the ability of the element to block the majority of current up to a certain level, but then, once that level is reached, the element allows the majority of the current over and above that level to flow.

摘要翻译： 公开了一种使用具有非线性IV特性的电阻性存储单元元件的可重写存储器。 在某些存储器阵列中非线性是重要的，以防止未选择的单元被干扰并减少所需的电流。 非线性是指元件将大多数电流阻塞到一定水平的能力，但是，一旦达到该电平，该元件允许超过该电平的大部分电流流动。

公开(公告)号：US06753561B1

公开(公告)日：2004-06-22

申请号：US10330512

申请日：2002-12-26

申请人： Darrell Rinerson ,  Steven W. Longcor ,  Edmond R. Ward ,  Steve Kuo-Ren Hsia ,  Wayne Kinney ,  Christophe J. Chevallier

发明人： Darrell Rinerson ,  Steven W. Longcor ,  Edmond R. Ward ,  Steve Kuo-Ren Hsia ,  Wayne Kinney ,  Christophe J. Chevallier

IPC分类号： H01L31062

CPC分类号： H01L27/2418 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/003 ,  G11C2213/31 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/147 ,  H01L45/165

摘要： Cross point memory array using multiple thin films. The invention is a cross point memory array that uses conductive array lines and multiple thin films as a memory plug. The thin films of the memory plug include a memory element and a non-ohmic device. The memory element switches between resistive states upon application of voltage pulses and the non-ohmic device imparts a relatively high resistance to the memory plug upon application of low magnitude voltages.

摘要翻译： 使用多个薄膜的交叉点存储阵列。 本发明是使用导电阵列线和多个薄膜作为存储器插头的交叉点存储器阵列。 存储器插头的薄膜包括存储器元件和非欧姆器件。 存储器元件在施加电压脉冲时在电阻状态之间切换，并且非欧姆器件在施加低幅度电压时对存储器插头施加相当高的电阻。

公开(公告)号：US20110155990A1

公开(公告)日：2011-06-30

申请号：US12932642

申请日：2011-03-01

申请人： Robin Cheung ,  Darrell Rinerson ,  Travis Byonghyop Oh ,  Jon Bornstein ,  David Hansen

发明人： Robin Cheung ,  Darrell Rinerson ,  Travis Byonghyop Oh ,  Jon Bornstein ,  David Hansen

IPC分类号： H01L45/00

CPC分类号： H01L27/101 ,  H01L27/2418 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1641 ,  H01L45/165

摘要： A structure for a memory device including a plurality of substantially planar thin-film layers or a plurality of conformal thin-film layers is disclosed. The thin-film layers form a memory element that is electrically in series with first and second cladded conductors and operative to store data as a plurality of conductivity profiles. A select voltage applied across the first and second cladded conductors is operative to perform data operations on the memory device. The memory device may optionally include a non-ohmic device electrically in series with the memory element and the first and second cladded conductors. Fabrication of the memory device does not require the plurality of thin-film layers be etched in order to form the memory element. The memory element can include a CMO layer having a selectively crystallized polycrystalline portion and an amorphous portion. The cladded conductors can include a core material made from copper.

公开(公告)号：US07888711B2

公开(公告)日：2011-02-15

申请号：US12803214

申请日：2010-06-21

申请人： Robin Cheung ,  Darrell Rinerson ,  Travis Byonghyop Oh ,  Jonathan Bornstein ,  David Hansen

发明人： Robin Cheung ,  Darrell Rinerson ,  Travis Byonghyop Oh ,  Jonathan Bornstein ,  David Hansen

IPC分类号： H01L29/66

CPC分类号： H01L27/101 ,  H01L27/2418 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1641 ,  H01L45/165 ,  Y10S257/903

摘要： A structure for a memory device including a plurality of substantially planar thin-film layers or a plurality of conformal thin-film layers is disclosed. The thin-film layers form a memory element that is electrically in series with first and second cladded conductors and operative to store data as a plurality of conductivity profiles. A select voltage applied across the first and second cladded conductors is operative to perform data operations on the memory device. The memory device may optionally include a non-ohmic device electrically in series with the memory element and the first and second cladded conductors. Fabrication of the memory device does not require the plurality of thin-film layers be etched in order to form the memory element. The memory element can include a CMO layer having a selectively crystallized polycrystalline portion and an amorphous portion. The cladded conductors can include a core material made from copper.

公开(公告)号：US07742323B2

公开(公告)日：2010-06-22

申请号：US11881474

申请日：2007-07-26

申请人： Darrell Rinerson ,  Jonathan Bornstein ,  Robin Cheung ,  David Hansen ,  Travis Byonghyop Oh

发明人： Darrell Rinerson ,  Jonathan Bornstein ,  Robin Cheung ,  David Hansen ,  Travis Byonghyop Oh

IPC分类号： G11C11/00

CPC分类号： H01L27/101 ,  H01L27/2418 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1641 ,  H01L45/165 ,  Y10S257/903

摘要： A structure for a memory device including a plurality of substantially planar thin-film layers or a plurality of conformal thin-film layers is disclosed. The thin-film layers form a memory element that is electrically in series with first and second cladded conductors and operative to store data as a plurality of conductivity profiles. A select voltage applied across the first and second cladded conductors is operative to perform data operations on the memory device. The memory device may optionally include a non-ohmic device electrically in series with the memory element and the first and second cladded conductors. Fabrication of the memory device does not require the plurality of thin-film layers be etched in order to form the memory element. The memory element can include a CMO layer having a selectively crystallized polycrystalline portion and an amorphous portion. The cladded conductors can include a core material made from copper.

摘要翻译： 公开了一种包括多个基本平坦的薄膜层或多个共形薄膜层的存储器件的结构。 薄膜层形成与第一和第二包覆导体电串联的存储元件，并且可操作以将数据存储为多个电导率分布。 施加在第一和第二包层导体上的选择电压用于在存储器件上执行数据操作。 存储器件可以可选地包括与存储元件和第一和第二包层导体串联电的非欧姆器件。 为了形成存储元件，存储器件的制造不需要蚀刻多个薄膜层。 存储元件可以包括具有选择性结晶的多晶部分和非晶部分的CMO层。 包层导体可以包括由铜制成的芯材料。