中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

149 records (took 0.023 seconds)

    Planar split-gate high-performance MOSFET structure and manufacturing method
    93.
    发明授权
    Planar split-gate high-performance MOSFET structure and manufacturing method 有权
    平面分闸高性能MOSFET结构及制造方法

    公开(公告)号：US08053298B2

    公开(公告)日：2011-11-08

    申请号：US12381813

    申请日：2009-03-16

    Applicant: Anup Bhalla ,  Francois Hebert ,  Daniel S. Ng

    Inventor： Anup Bhalla ,  Francois Hebert ,  Daniel S. Ng

    IPC: H01L21/337

    CPC classification number: H01L29/7802 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/66712 ,  H01L29/7828

    Abstract: This invention discloses an improved semiconductor power device includes a plurality of power transistor cells wherein each cell further includes a planar gate padded by a gate oxide layer disposed on top of a drift layer constituting an upper layer of a semiconductor substrate wherein the planar gate further constituting a split gate including a gap opened in a gate layer whereby the a total surface area of the gate is reduced. The transistor cell further includes a JFET (junction field effect transistor) diffusion region disposed in the drift layer below the gap of the gate layer wherein the JFET diffusion region having a higher dopant concentration than the drift region for reducing a channel resistance of the semiconductor power device. The transistor cell further includes a shallow surface doped regions disposed near a top surface of the drift layer under the gate adjacent to the JFET diffusion region wherein the shallow surface doped region having a dopant concentration lower than the JFET diffusion region and higher than the drift layer.

    Abstract translation: 本发明公开了一种改进的半导体功率器件，包括多个功率晶体管单元，其中每个单元还包括由设置在构成半导体衬底的上层的漂移层的顶部上的栅极氧化物层填充的平面栅极，其中平面栅极进一步构成 分闸门，其包括在栅极层中开口的间隙，由此栅极的总表面积减小。 晶体管单元还包括设置在栅极层间隙之下的漂移层中的JFET（结场效应晶体管）扩散区，其中具有比漂移区更高的掺杂浓度的JFET扩散区用于降低半导体功率的沟道电阻 设备。 晶体管单元还包括在邻近JFET扩散区的栅极附近设置在漂移层的顶表面附近的浅表面掺杂区，其中掺杂浓度低于JFET扩散区并且高于漂移层的浅表面掺杂区 。

    GaN BASED POWER DEVICES WITH INTEGRATED PROTECTION DEVICES: STRUCUTRES AND METHODS
    94.
    发明申请
    GaN BASED POWER DEVICES WITH INTEGRATED PROTECTION DEVICES: STRUCUTRES AND METHODS 失效
    具有集成保护装置的GaN基功率器件：结构和方法

    公开(公告)号：US20110260216A1

    公开(公告)日：2011-10-27

    申请号：US12950453

    申请日：2010-11-19

    Applicant: Francois Hebert

    Inventor： Francois Hebert

    IPC: H01L29/778 ,  H01L21/335

    CPC classification number: H01L27/0255 ,  H01L21/8258 ,  H01L27/0629 ,  H01L27/0688 ,  H01L29/0619 ,  H01L29/0653 ,  H01L29/1075 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/8611 ,  H01L29/872

    Abstract: Exemplary embodiments provide structures and methods for power devices with integrated clamp structures. The integration of clamp structures can protect the power device, e.g., from electrical overstress (EOS). In one embodiment, active devices can be formed over a substrate, while a clamp structure can be integrated outside the active regions of the power device, for example, under the active regions and/or inside the substrate. Integrating clamp structure outside active regions of power devices can maximize the active area for a given die size and improve robustness of the clamped device since the current will spread in the substrate by this integration.

    Abstract translation: 示例性实施例提供了具有集成钳位结构的功率器件的结构和方法。 夹紧结构的集成可以保护功率器件，例如不受电力过应力（EOS）的影响。 在一个实施例中，有源器件可以形成在衬底上，而钳位结构可以集成在功率器件的有源区域外部，例如在有源区域下方和/或衬底内部。 在功率器件的有源区域之外集成钳位结构可以使给定管芯尺寸的有效面积最大化，并且改善钳位器件的鲁棒性，因为电流将通过该积分在衬底中扩展。

    BOTTOM-DRAIN LDMOS POWER MOSFET STRUCTURE HAVING A TOP DRAIN STRAP
    99.
    发明申请
    BOTTOM-DRAIN LDMOS POWER MOSFET STRUCTURE HAVING A TOP DRAIN STRAP 有权
    底部排水LDMOS功率MOSFET结构具有顶部排水带

    公开(公告)号：US20110014766A1

    公开(公告)日：2011-01-20

    申请号：US12891485

    申请日：2010-09-27

    Applicant: Francois Hebert

    Inventor： Francois Hebert

    IPC: H01L21/336

    CPC classification number: H01L29/0847 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/66659 ,  H01L29/7835

    Abstract: Lateral DMOS devices having improved drain contact structures and methods for making the devices are disclosed. A semiconductor device comprises a semiconductor substrate; an epitaxial layer on top of the substrate; a drift region at a top surface of the epitaxial layer; a source region at a top surface of the epitaxial layer; a channel region between the source and drift regions; a gate positioned over a gate dielectric on top of the channel region; and a drain contact trench that electrically connects the drift layer and substrate. The contact trench includes a trench formed vertically from the drift region, through the epitaxial layer to the substrate and filled with an electrically conductive drain plug; electrically insulating spacers along sidewalls of the trench; and an electrically conductive drain strap on top of the drain contact trench that electrically connects the drain contact trench to the drift region.

    Abstract translation: 公开了具有改进的漏极接触结构的侧面DMOS器件和用于制造器件的方法。 半导体器件包括半导体衬底; 在衬底的顶部上的外延层; 位于外延层顶表面的漂移区; 在所述外延层的顶表面处的源极区; 源极和漂移区域之间的沟道区域; 栅极位于沟道区域顶部的栅极电介质上; 以及电连接漂移层和衬底的漏极接触沟槽。 接触沟槽包括从漂移区垂直形成的沟槽，穿过外延层到衬底并填充有导电排放塞; 沿沟槽侧壁的电绝缘垫片; 以及在漏极接触沟槽的顶部上的导电漏极带，其将漏极接触沟槽电连接到漂移区域。

Patent Agency Ranking