利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

409 条记录 (耗时 0.022 秒)

    Planar split-gate high-performance MOSFET structure and manufacturing method
    2.
    发明授权
    Planar split-gate high-performance MOSFET structure and manufacturing method 有权
    平面分闸高性能MOSFET结构及制造方法

    公开(公告)号：US08053298B2

    公开(公告)日：2011-11-08

    申请号：US12381813

    申请日：2009-03-16

    申请人： Anup Bhalla ,  Francois Hebert ,  Daniel S. Ng

    发明人： Anup Bhalla ,  Francois Hebert ,  Daniel S. Ng

    IPC分类号： H01L21/337

    CPC分类号： H01L29/7802 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/66712 ,  H01L29/7828

    摘要： This invention discloses an improved semiconductor power device includes a plurality of power transistor cells wherein each cell further includes a planar gate padded by a gate oxide layer disposed on top of a drift layer constituting an upper layer of a semiconductor substrate wherein the planar gate further constituting a split gate including a gap opened in a gate layer whereby the a total surface area of the gate is reduced. The transistor cell further includes a JFET (junction field effect transistor) diffusion region disposed in the drift layer below the gap of the gate layer wherein the JFET diffusion region having a higher dopant concentration than the drift region for reducing a channel resistance of the semiconductor power device. The transistor cell further includes a shallow surface doped regions disposed near a top surface of the drift layer under the gate adjacent to the JFET diffusion region wherein the shallow surface doped region having a dopant concentration lower than the JFET diffusion region and higher than the drift layer.

    摘要翻译： 本发明公开了一种改进的半导体功率器件，包括多个功率晶体管单元，其中每个单元还包括由设置在构成半导体衬底的上层的漂移层的顶部上的栅极氧化物层填充的平面栅极，其中平面栅极进一步构成 分闸门，其包括在栅极层中开口的间隙，由此栅极的总表面积减小。 晶体管单元还包括设置在栅极层间隙之下的漂移层中的JFET（结场效应晶体管）扩散区，其中具有比漂移区更高的掺杂浓度的JFET扩散区用于降低半导体功率的沟道电阻 设备。 晶体管单元还包括在邻近JFET扩散区的栅极附近设置在漂移层的顶表面附近的浅表面掺杂区，其中掺杂浓度低于JFET扩散区并且高于漂移层的浅表面掺杂区 。

    Inverted-trench grounded-source FET structure with trenched source body short electrode
    4.
    发明申请
    Inverted-trench grounded-source FET structure with trenched source body short electrode 有权
    反沟槽接地源FET结构，具有沟槽源体短路电极

    公开(公告)号：US20080067584A1

    公开(公告)日：2008-03-20

    申请号：US11522669

    申请日：2006-09-17

    申请人： Sik K Lui ,  Francois Hebert ,  Anup Bhalla

    发明人： Sik K Lui ,  Francois Hebert ,  Anup Bhalla

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/781 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L2924/0002 ,  H01L2924/00

    摘要： This invention discloses bottom-source lateral diffusion MOS (BS-LDMOS) device. The device has a source region disposed laterally opposite a drain region near a top surface of a semiconductor substrate supporting a gate thereon between the source region and a drain region. The BS-LDMOS device further has a combined sinker-channel region disposed at a depth in the semiconductor substrate entirely below a body region disposed adjacent to the source region near the top surface wherein the combined sinker-channel region functioning as a buried source-body contact for electrically connecting the body region and the source region to a bottom of the substrate functioning as a source electrode. A drift region is disposed near the top surface under the gate and at a distance away from the source region and extending to and encompassing the drain region. The combined sinker-channel region extending below the drift region and the combined sinker-channel region that has a dopant-conductivity opposite to and compensating the drift region for reducing the source-drain capacitance.

    摘要翻译： 本发明公开了底源横向扩散MOS（BS-LDMOS）器件。 器件具有在半导体衬底的顶表面附近的漏区附近设置的源极区域，该半导体衬底在源极区域和漏极区域之间支撑栅极。 BS-LDMOS器件还具有一个组合的沉陷通道区域，该半导体衬底的深度完全位于靠近顶表面的源极区域附近设置的体区域之下，其中组合沉降通道区域用作掩埋源体 用于将主体区域和源区域电连接到用作源电极的衬底的底部。 漂移区域设置在栅极下方的顶表面附近并且远离源极区域并且延伸到并包围漏极区域。 在漂移区域下方延伸的组合沉降通道区域和具有与掺杂剂 - 导电性相反并补偿漂移区域以减少源极 - 漏极电容的组合沉降沟道区域。

    Self-aligned slotted accumulation-mode field effect transistor (AccuFET) structure and method
    8.
    发明申请
    Self-aligned slotted accumulation-mode field effect transistor (AccuFET) structure and method 有权
    自对准开槽积分型场效应晶体管（AccuFET）结构及方法

    公开(公告)号：US20090218619A1

    公开(公告)日：2009-09-03

    申请号：US12074280

    申请日：2008-03-02

    申请人： Francois Hebert ,  Madhur Bobde ,  Anup Bhalla

    发明人： Francois Hebert ,  Madhur Bobde ,  Anup Bhalla

    IPC分类号： H01L29/739 ,  H01L21/3205

    CPC分类号： H01L29/7828 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0847 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/66666

    摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device includes trenched gates each having a stick-up gate segment extended above a top surface of the semiconductor substrate surrounded by sidewall spacers. The semiconductor power device further includes slots opened aligned with the sidewall spacers substantially parallel to the trenched gates. The stick-up gate segment further includes a cap composed of an insulation material surrounded by the sidewall spacers. A layer of barrier metal covers a top surface of the cap and over the sidewall spacers and extends above a top surface of the slots. The slots are filled with a gate material same as the gate segment for functioning as additional gate electrodes for providing a depletion layer extends toward the trenched gates whereby a drift region between the slots and the trenched gate is fully depleted at a gate-to-drain voltage Vgs=0 volt.

    摘要翻译： 本发明公开了一种设置在半导体衬底中的半导体功率器件。 半导体功率器件包括沟槽栅极，每个沟槽栅极具有在由侧壁间隔物围绕的半导体衬底的顶表面之上延伸的伸出栅极段。 半导体功率器件还包括与基本上平行于沟槽栅极的侧壁间隔开的开口的槽。 粘贴门区段还包括由侧壁间隔物围绕的绝缘材料构成的盖。 阻挡金属层覆盖盖的顶表面并且覆盖在侧壁间隔物上并在槽的顶表面上方延伸。 这些槽填充有与栅极段相同的栅极材料，用作附加栅电极，用于提供向沟槽栅极延伸的耗尽层，借此栅极与沟槽栅极之间的漂移区域完全耗尽栅极 - 漏极 电压Vgs = 0伏。

    Planar split-gate high-performance MOSFET structure and manufacturing method
    9.
    发明申请
    Planar split-gate high-performance MOSFET structure and manufacturing method 有权
    平面分闸高性能MOSFET结构及制造方法

    公开(公告)号：US20090181503A1

    公开(公告)日：2009-07-16

    申请号：US12381813

    申请日：2009-03-16

    申请人： Anup Bhalla ,  Francois Hebert ,  Daniel S. Ng

    发明人： Anup Bhalla ,  Francois Hebert ,  Daniel S. Ng

    IPC分类号： H01L21/337

    CPC分类号： H01L29/7802 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/66712 ,  H01L29/7828

    摘要： This invention discloses an improved semiconductor power device includes a plurality of power transistor cells wherein each cell further includes a planar gate padded by a gate oxide layer disposed on top of a drift layer constituting an upper layer of a semiconductor substrate wherein the planar gate further constituting a split gate including a gap opened in a gate layer whereby the a total surface area of the gate is reduced. The transistor cell further includes a JFET (junction field effect transistor) diffusion region disposed in the drift layer below the gap of the gate layer wherein the JFET diffusion region having a higher dopant concentration than the drift region for reducing a channel resistance of the semiconductor power device. The transistor cell further includes a shallow surface doped regions disposed near a top surface of the drift layer under the gate adjacent to the JFET diffusion region wherein the shallow surface doped region having a dopant concentration lower than the JFET diffusion region and higher than the drift layer.

    摘要翻译： 本发明公开了一种改进的半导体功率器件，包括多个功率晶体管单元，其中每个单元还包括由设置在构成半导体衬底的上层的漂移层的顶部上的栅极氧化物层填充的平面栅极，其中平面栅极进一步构成 分闸门，其包括在栅极层中开口的间隙，由此栅极的总表面积减小。 晶体管单元还包括设置在栅极层间隙之下的漂移层中的JFET（结场效应晶体管）扩散区，其中具有比漂移区更高的掺杂浓度的JFET扩散区用于降低半导体功率的沟道电阻 设备。 晶体管单元还包括在邻近JFET扩散区的栅极附近设置在漂移层的顶表面附近的浅表面掺杂区，其中掺杂浓度低于JFET扩散区并且高于漂移层的浅表面掺杂区 。