公开(公告)号：US20090267883A1

公开(公告)日：2009-10-29

申请号：US12318301

申请日：2008-12-24

申请人： Jin-Ho Kim ,  Houg-Jae Shin

发明人： Jin-Ho Kim ,  Houg-Jae Shin

IPC分类号： G09G3/36

CPC分类号： G09G3/3677 ,  G09G2300/0417 ,  G09G2320/0223

摘要： A driving circuit of a liquid crystal display includes: a timing controller to output a gate control signal and a data control signal to control driving of a gate driving unit and a data driving unit and to output digital video data; a pair of gate driving units to be alternately driven by using at least one frame as a period to supply gate signals to gate lines of a liquid crystal panel in-response to the gate control signal; and a data driving unit to supply pixel signals to data lines of the liquid crystal panel in response to the data control signal. Degradation of characteristics of transistors constituting each gate driver can be prevented.

摘要翻译： 液晶显示器的驱动电路包括：时序控制器，用于输出栅极控制信号和数据控制信号，以控制栅极驱动单元和数据驱动单元的驱动并输出数字视频数据; 一对栅极驱动单元，通过使用至少一个帧作为周期来交替驱动，以响应于栅极控制信号向液晶面板的栅极线提供栅极信号; 以及数据驱动单元，用于响应于数据控制信号将像素信号提供给液晶面板的数据线。 可以防止构成每个栅极驱动器的晶体管的特性的降低。

公开(公告)号：US07570335B2

公开(公告)日：2009-08-04

申请号：US11239002

申请日：2005-09-30

申请人： Jin-Ho Kim ,  Sung-O Moon

发明人： Jin-Ho Kim ,  Sung-O Moon

IPC分类号： G02F1/1343

CPC分类号： G02F1/134363 ,  G02F1/133528

摘要： An in-plane switching liquid crystal display device includes a first substrate, a second substrate spaced apart from the first substrate, a liquid crystal layer between the first and second substrates, a first polarizer at an outer surface of the first substrate, the first polarizer including a first polarization film and first inner and outer supporting film at both sides of the first polarization film, the first inner supporting film adjacent to the first substrate and having a retardation within a range of about −10 nm to about +10 nm, and a second polarizer at an outer surface of the second substrate, the second polarizer including a second polarization film and second inner and outer supporting film at both sides of the second polarization film, the second inner supporting film adjacent to the second substrate.

摘要翻译： 面内切换液晶显示装置包括第一基板，与第一基板间隔开的第二基板，第一基板与第二基板之间的液晶层，第一基板的外表面的第一偏振片，第一偏振片 包括第一偏振膜和在第一偏振膜的两侧的第一内支撑膜和第二内支撑膜，第一内支撑膜与第一基板相邻，并且在约-10nm至约+ 10nm的范围内具有延迟，以及 在第二基板的外表面处的第二偏振器，第二偏振器包括第二偏振膜和在第二偏振膜两侧的第二内支撑膜和第二内支撑膜，第二内支撑膜邻近第二基板。

公开(公告)号：US20080312515A1

公开(公告)日：2008-12-18

申请号：US12000038

申请日：2007-12-07

申请人： Chan-Hyun Youn ,  Chang-Hee Han ,  Youngjoo Han ,  Byung-Jin Kim ,  Jin-Ho Kim ,  Eun Bo Shim

发明人： Chan-Hyun Youn ,  Chang-Hee Han ,  Youngjoo Han ,  Byung-Jin Kim ,  Jin-Ho Kim ,  Eun Bo Shim

IPC分类号： A61B5/00

CPC分类号： A61B5/0006 ,  A61B5/04007 ,  A61B5/0464 ,  G06Q50/22

摘要： System and method provide an on-line high-performance diagnosis service for cardiovascular disorders. A client requests a high-performance diagnosis by transmitting real electrocardiographic treatment data and magnetocardiographic treatment data of a human body being a treatment object and virtual heart simulation parameters to a medical service server. The medical service server, in response to the diagnosis request, analyzes the real electrocardiographic treatment data to generate an electrocardiographic analysis result, and performs a virtual heart simulation using the simulation parameters to generate a pseudo electrocardiogram and magnetocardiogram. Further, the medical service server determines a disease state of the human body on the basis of the electrocardiographic analysis result, the magnetocardiographic treatment data and the pseudo electrocardiogram and magnetocardiogram, and generates definitive diagnosis data through comparison among the real magnetocardiographic treatment data, the electrocardiographic analysis result, the disease state, and a diagnosis criteria. The definitive diagnosis data is provided to the client.

摘要翻译： 系统和方法为心血管疾病提供在线高性能诊断服务。 客户通过将作为治疗对象的人体的实际心电图治疗数据和磁心处理数据和虚拟心脏模拟参数传送到医疗服务器来请求高性能诊断。 医疗服务服务器响应于诊断请求，分析实际的心电图处理数据以产生心电图分析结果，并使用仿真参数进行虚拟心脏模拟，以产生伪心电图和心电图。 此外，医疗服务服务器基于心电图分析结果，磁心处理数据和伪心电图和磁心电图来确定人体的疾病状态，并且通过在真实磁心治疗数据，心电图之间进行比较来生成确定的诊断数据 分析结果，疾病状态和诊断标准。 确定的诊断数据提供给客户端。

公开(公告)号：USD576325S1

公开(公告)日：2008-09-02

申请号：US29287857

申请日：2007-09-27

申请人： Jin-Ho Kim ,  Sang-Cheon Jeon ,  Shung-Hoon Hwang

设计人： Jin-Ho Kim ,  Sang-Cheon Jeon ,  Shung-Hoon Hwang

公开(公告)号：US20080181247A1

公开(公告)日：2008-07-31

申请号：US12011325

申请日：2008-01-25

申请人： Jin-Ho Kim ,  Jin-Young Bae ,  Chae-Yong Chong ,  Sang-Young Lee

发明人： Jin-Ho Kim ,  Jin-Young Bae ,  Chae-Yong Chong ,  Sang-Young Lee

IPC分类号： H04L12/56

CPC分类号： H04L49/9047 ,  H04L49/90 ,  H04L49/901

摘要： Queue processing method and apparatus in a network system are provided. The queue processing method in a network system includes when a packet is input to a buffer, checking whether the buffer belongs to the same memory channel; when the buffer does not belong to the same memory channel, converting an address of a buffer descriptor about the packet to an address of a next packet address storage of the same channel of a queue; and enqueuing the converted address.

摘要翻译： 提供了网络系统中的队列处理方法和装置。 网络系统中的队列处理方法包括：当分组被输入缓冲器时，检查缓冲区是否属于同一个存储信道; 当缓冲器不属于相同的存储器通道时，将关于分组的缓冲器描述符的地址转换为队列的同一信道的下一个分组地址存储的地址; 并排列转换的地址。

公开(公告)号：US07368821B2

公开(公告)日：2008-05-06

申请号：US11231751

申请日：2005-09-22

申请人： Sang-Young Kim ,  Jin-Ho Kim ,  Hee-Jin Park ,  Young-Hee Song ,  Tae-Sung Yoon

发明人： Sang-Young Kim ,  Jin-Ho Kim ,  Hee-Jin Park ,  Young-Hee Song ,  Tae-Sung Yoon

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L23/49816 ,  H01L23/3128 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/303 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/094 ,  H05K2201/09781 ,  H05K2201/10734 ,  H05K2201/2036 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： In example embodiments of the present invention, a structure of a BGA semiconductor chip package includes a substrate having first and second surfaces, a semiconductor chip having a plurality of bonding pads, and mounted on the first surface of the substrate, and plurality of in/out (I/O) solder balls and dummy solder balls provided on the second surface of the substrate, wherein the I/O solder balls are electrically connected to the semiconductor chip and the dummy solder balls are electrically isolated from the semiconductor chip, and the I/O solder balls and the dummy solder balls have the same ball size and ball pitch and are uniformly provided over the second surface of the substrate.

摘要翻译： 在本发明的示例性实施例中，BGA半导体芯片封装的结构包括具有第一和第二表面的衬底，具有多个焊盘的半导体芯片，并且安装在衬底的第一表面上，以及多个入/ （I / O）焊球和设置在基板的第二表面上的虚拟焊球，其中I / O焊球电连接到半导体芯片，并且虚拟焊球与半导体芯片电隔离，并且 I / O焊球和虚拟焊球具有相同的球尺寸和球间距，并均匀地设置在基板的第二表面上。

公开(公告)号：US20080085581A1

公开(公告)日：2008-04-10

申请号：US11647722

申请日：2006-12-29

申请人： Jin-Ho Kim ,  Jae-Kwan Park ,  Dong-Hwa Kwak ,  Su-Jin Ahn ,  Yoon-Moon Park ,  Jue-Hwang Sim ,  Jang-Ho Park ,  Sang-Yong Park

发明人： Jin-Ho Kim ,  Jae-Kwan Park ,  Dong-Hwa Kwak ,  Su-Jin Ahn ,  Yoon-Moon Park ,  Jue-Hwang Sim ,  Jang-Ho Park ,  Sang-Yong Park

IPC分类号： H01L21/8242

CPC分类号： H01L27/11568 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L27/105

摘要： Patterns are formed in a semiconductor device by defining a lower layer that includes a first region and a second region on a semiconductor substrate, forming first patterns with a first pitch that extend to the first and second regions, forming second patterns with a second pitch in the second region that are alternately arranged with the first patterns, forming a space insulating layer that covers the first and second patterns and comprises gap regions that are alternately arranged with the first patterns so as to correspond with the second patterns, forming third patterns that correspond to the second patterns in the gap regions, respectively, etching the space insulating layer between the first and second patterns and between the first and third patterns, such that the space insulating layer remains between the second patterns and the third patterns, and etching the lower layer using the first, second, and third patterns and the remaining space insulating layer between the second and third patterns as an etching mask.

公开(公告)号：US20070120171A1

公开(公告)日：2007-05-31

申请号：US11246447

申请日：2005-10-06

申请人： Yue-Song He ,  Chung Leung ,  Jin-Ho Kim ,  Kwok Ng

发明人： Yue-Song He ,  Chung Leung ,  Jin-Ho Kim ,  Kwok Ng

IPC分类号： H01L29/788

CPC分类号： H01L29/42336 ,  G11C16/0458 ,  G11C16/0491 ,  H01L27/115 ,  H01L27/11521

摘要： A memory cell (110) has a plurality of floating gates (120L, 120R). The channel region (170) comprises a plurality of sub-regions (220L, 220R) adjacent to the respective floating gates, and a connection region (210) between the floating gates. The connection region has the same conductivity type as the source/drain regions (160) to increase the channel conductivity. Therefore, the floating gates can be brought closer together even though the inter-gate dielectric (144) becomes thick between the floating gates, weakening the control gate's (104) electrical field in the channel.

摘要翻译： 存储单元（110）具有多个浮动栅极（120L，120R）。 通道区域（170）包括与相应浮动栅极相邻的多个子区域（220L，220R），以及浮置栅极之间的连接区域（210）。 连接区域具有与源极/漏极区域（160）相同的导电类型以增加沟道导电性。 因此，即使栅极间电介质（144）在浮置栅极之间变厚，削弱了沟道中的控制栅极（104）电场，浮动栅极也可以更靠近在一起。

公开(公告)号：US20070045175A1

公开(公告)日：2007-03-01

申请号：US11211889

申请日：2005-08-24

申请人： Moon-Seog Jang ,  Sung-Soo Kim ,  Myung-Nam Han ,  Jin-Ho Kim ,  Min-Soo Park

发明人： Moon-Seog Jang ,  Sung-Soo Kim ,  Myung-Nam Han ,  Jin-Ho Kim ,  Min-Soo Park

IPC分类号： B01D71/26

CPC分类号： B01D71/26 ,  B01D67/0088 ,  B01D69/08 ,  B01D69/087 ,  B01D2323/08 ,  B01D2323/14 ,  B01D2323/26 ,  B01D2323/42 ,  B01D2325/02

摘要： A porous polyethylene hollow fiber membrane having a pore-size gradient across the inner and outer surfaces thereof is prepared by introducing, during the cooling step of a melt-spun polyethylene hollow fiber, a nitrogen flow and a solvent having a boiling point in the range of 30 to 80° C. to the inner and outer surfaces of the melt-spun hollow fiber, respectively.

摘要翻译： 在熔融纺丝的聚乙烯中空纤维的冷却步骤中，通过将沸点在该范围内的氮气流和溶剂引入，制备其内表面和外表面上具有孔径梯度的多孔聚乙烯中空纤维膜 分别为熔融中空纤维的内表面和外表面30至80℃。

公开(公告)号：US07071115B2

公开(公告)日：2006-07-04

申请号：US10772932

申请日：2004-02-04

申请人： Chunchieh Huang ,  Chia-Shun Hsiao ,  Jin-Ho Kim ,  Kuei-Chang Tsai ,  Barbara Haselden ,  Daniel C. Wang

发明人： Chunchieh Huang ,  Chia-Shun Hsiao ,  Jin-Ho Kim ,  Kuei-Chang Tsai ,  Barbara Haselden ,  Daniel C. Wang

IPC分类号： H01L21/302 ,  H01L21/461 ,  H01L21/44 ,  H01L21/76

CPC分类号： H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11539

摘要： In integrated circuit fabrication, an etch is used that has a lateral component. For example, the etch may be isotropic. Before the isotropic etch of a layer (160), another etch of the same layer is performed. This other etch can be anisotropic. This etch attacks a portion (160X2) of the layer adjacent to the feature to be formed by the isotropic etch. That portion is entirely or partially removed by the anisotropic etch. Then the isotropic etch mask (420) is formed to extend beyond the feature over the location of the portion subjected to the anisotropic etch. If that portion was removed entirely, then the isotropic etch mask may completely seal off the feature to be formed on the side of that portion, so the lateral etching will not occur. If that portion was removed only partially, then the lateral undercut will be impeded because the passage to the feature under the isotropic etch mask will be narrowed.